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Design >> Analog Design >> settling time
https://designers-guide.org/forum/YaBB.pl?num=1333661815

Message started by medya on Apr 5^th, 2012, 2:36pm

Title: settling time
Post by medya on Apr 5^th, 2012, 2:36pm

Hi,
I obtain so different values for settling time of dfferential and single output of my desiged OTA that use it in an ideal switch cap circuit!!!what is the problem???the accuracy is 0.024%.result are for same simulation.(plz see the attached pic).
thx.

Title: Re: settling time
Post by Garrett.Neaves on Apr 5^th, 2012, 4:28pm

Your picture appears to not be attached.

Garrett

Title: Re: settling time
Post by medya on Apr 5^th, 2012, 10:08pm

I'm sorry for this mistake.