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Design >> Analog Design >> DC offset cancellation
https://designers-guide.org/forum/YaBB.pl?num=1334250418

Message started by raja.cedt on Apr 12^th, 2012, 10:06am

Title: DC offset cancellation
Post by raja.cedt on Apr 12^th, 2012, 10:06am

hello all,
i had question regarding DC cancellation loop for trans-impedance amplifier. The low cutoff frequency for this loop is 80K, so i have to use really big R and C (and i have seen many publication where most of the people are going for off-chip). So why no one is trying to amplify capacitors by miller in this case?

Thanks,
raj.

Title: Re: DC offset cancellation
Post by loose-electron on Apr 13^th, 2012, 8:30pm

Consider using a digital feedback method, so you don't need a huge integration filter-cap

counter - DAC - detector and averaging.

Title: Re: DC offset cancellation
Post by aaron_do on Apr 15^th, 2012, 6:53am

Hi Loose-electron,

could you explain that a bit (counter-DAC-detector and averaging)?

Seems like you need an ADC somewhere, and if so, does it need an anti-aliasing filter?

I remember seeing a paper a while ago which used sigma-delta ADCs to detect the DC offset for correction. Sorry I don't know much about why people don't use miller amplification of capacitance...

Aaron

Title: Re: DC offset cancellation
Post by loose-electron on Apr 16^th, 2012, 8:33pm

Analog method integration feedback require the big C.

Digital method looks at the average value out of the device. That requires a comparator and a method of averaging which gets rid of the signal and leave you with just the offsets.
If the signal on top of the offset is DC balanced (most are) that comparator, with lots of averaging will indicate if the offset is high or low.

That averaging is now a digital process, and can be digitally processed to index up or down the value controlling a DAC, which is summed in to cancel the offset at the input of the device.

It is still a control system loop with the detection and the feedback being analog, but everything between those two points being digital.

Title: Re: DC offset cancellation
Post by aaron_do on Apr 17^th, 2012, 2:41am

Hi loose-electron,

thanks for the info. If I understand it correctly, you need to run the comparator >2x the signal bandwidth otherwise you will have aliasing issues. Does that sound correct? Otherwise you could just run the comparator very slow since you are only concerned with the DC information anyway.

As I mentioned, a paper I read a while back used sigma-delta converters to sense the DC offset. Perhaps they were using continuous-time sigma-delta converters which have some inherent anti-alising? Do you think that would work?

thanks,
Aaron

Title: Re: DC offset cancellation
Post by loose-electron on Apr 18^th, 2012, 8:12pm

You can strip the modulation away from the DC offset using a duty cycle method from a comparator. When the duty cycle is 50% on average, the offset is removed.

Averaging can be by LPF (big size filter) or digital counting methods (smaller due to using digital count-memory methods)

Title: Re: DC offset cancellation
Post by aaron_do on Apr 19^th, 2012, 8:08am

Hi loose-electron,

I understand your method, but I don't think it solves the aliasing issue. For instance, if the signal is a simple square wave with a frequency of 2x the comparator sampling frequency, then it will be interpreted as a DC offset.

Some filtering is probably necessary before the sampling...

Regards,
Aaron

Title: Re: DC offset cancellation
Post by loose-electron on Apr 22^nd, 2012, 8:56pm

digital averages are the same as analog LPF

If I stick a sine wave plus some DC offset into a comparator, the duty cycle will indicate the offset.

Average that with a digital circuit and if it is high or low and you have an offset indicator.

Use the offset indicator to move a DAC up-down as a summation tool to cancel the offset.

Its a control system problem essentially.

Title: Re: DC offset cancellation
Post by aaron_do on Apr 22^nd, 2012, 10:20pm

Hi loose-electron,

I understand the general principle of what you're saying. I just don't see how you can escape the aliasing problem. Unless you're telling me the digital portion is somehow not clocked. But then I can't see how you can average in the time-domain...

Even a sinewave + a DC offset can give the wrong DC offset if you sample the sine wave less than 2x the sine-wave frequency. Is there something I'm missing?

thanks,
Aaron

Title: Re: DC offset cancellation
Post by RobG on Apr 23^rd, 2012, 9:05am

Raja - a while back I spoke a little about miller multiplication. You are somewhat limited by the swing at the output of the amplifier. For example, for a 1.8V supply you can't have a multiplier of 100 if your input ripple is 20mVpp because the swing at the output of your amp will be 2Vpp. There are also issues of noise, how you are going to handle the DC bias on the input side of the cap, and whether or not the amplifier will be bigger than the circuit itself.

I'm not sure a digital solution is going to be smaller than just using a big cap. It will also introduce it's own ripple that will have to be filtered. Depending on the desired accuracy, I expect you will need an anti-aliasing filter in the FB path, but I don't think that would be much of a problem. [edit, I see Jerry speaks of a digital counting method to avoid the analog LPF, so the output may not need to be filtered, and the aliasing might average out, except for the components aliased to DC. But I'm not sure I completely understand how to realize that digital solution.]

You can decrease the F3db of the DC null path by lowering the DC gain of the amplifier used in the feedback path. Also, a gate cap + MIM cap can be used for the LPF so it will be relatively small.

Title: Re: DC offset cancellation
Post by raja.cedt on Apr 23^rd, 2012, 9:20am

hello..
robg you are correct, even i found the same(i just designed one multiplier with gain 100, in ac sim i have good phase margin but when i go to tran i got ringing probably it is not multiplying due to op amp saturation). I didn't get you "how you are going to handle the DC bias on the input side of the cap". One more thing what is the noise problem you are saying. Could you please tel me is there scenario where people were realized miller multiplication?
Thanks,
raj.

Title: Re: DC offset cancellation
Post by RobG on Apr 23^rd, 2012, 9:37am

Raja - the fact that I can't recall anywhere that Miller has worked very well also tells me that there must be additional issues (except for miller compensation of course).

What I meant about the DC input is that the capacitor normally has a DC value across it that is used to cancel the offset of the main amplifier. This DC bias is applied directly to one of the inputs of the main amplifier. This is the same node that you would put your Miller amplifier on, so I'm not sure how you would prevent the DC from getting gained up without additional circuitry.

Also, since the Miller amplifier is placed at one of the inputs to the main amplifier, I'm fairly certain the input-referred noise of the Miller amplifier is injected right into the main amplifier input.

rg

Title: Re: DC offset cancellation
Post by aaron_do on Apr 23^rd, 2012, 6:14pm

BTW, I'm not saying that aliasing is going to kill the digital method or anything like that, I'm just pointing out that it may be necessary if you intend to go that route.

Aaron

Title: Re: DC offset cancellation
Post by loose-electron on Apr 23^rd, 2012, 8:14pm

RobG wrote on Apr 23^rd, 2012, 9:05am:

I'm not sure a digital solution is going to be smaller than just using a big cap. It will also introduce it's own ripple that will have to be filtered. Depending on the desired accuracy, I expect you will need an anti-aliasing filter in the FB path, but I don't think that would be much of a problem. [edit, I see Jerry speaks of a digital counting method to avoid the analog LPF, so the output may not need to be filtered, and the aliasing might average out, except for the components aliased to DC. But I'm not sure I completely understand how to realize that digital solution.]

Yikes. The area taken by an integration capacitor will be huge.

This method gets used in GSM receivers for many years with the offset setting frozen for the TDMX cycle. (Adjust while transmitting, freeze setting while receiving.)

It also gets used to cancel offset in WCDMA receivers. (dynamic adjustment all the time)

Those are the two that I have done.

The magnitude of the LSB summing into the feedback point is a small amount of the signal, so that the feedback system provides small incremental adjustments.

Suggestion if you are having trouble visualizing this.

Start with an analog feedback model, start bring pieces of into the Z domain. When you get done, you can get it down to a comparator on the output and a summation DAC at the input. Everything else is logic. Less space, less power.

Title: Re: DC offset cancellation
Post by Lex on Apr 24^th, 2012, 1:41am

So you have 80 kHz cutoff frequency. That would require like 2 MegaOhm resistor and 10 pF capacitor? I suppose the cap doesn't need to be that linear, so you could use MOS to save on area. Ask for high resistive poly layer at your bosses desk. I think it should be okay in terms of area. I/We don't know how critical area is in your case. And of course 1 big advantage: it's simple ;)

But I like the digital filter too. You can make the cut off frequency programmable which gives you the flexibility to change it when the chip comes back from the fab.

Title: Re: DC offset cancellation
Post by RobG on Apr 24^th, 2012, 6:21am

loose-electron wrote on Apr 23^rd, 2012, 8:14pm:

This method gets used in GSM receivers for many years with the offset setting frozen for the TDMX cycle. (Adjust while transmitting, freeze setting while receiving.)

OK, I understand what you are doing now. I didn't realize you were holding the correction value since that hasn't been an option for me (excepting when you ping-pong between two zeroed amps). Yes, that would be probably be better if you have two different modes.

Title: Re: DC offset cancellation
Post by loose-electron on Apr 24^th, 2012, 2:29pm

RobG wrote on Apr 24^th, 2012, 6:21am:

loose-electron wrote on Apr 23^rd, 2012, 8:14pm:

This method gets used in GSM receivers for many years with the offset setting frozen for the TDMX cycle. (Adjust while transmitting, freeze setting while receiving.)

Like I said - you can also do it in a continuous mode ,
as long as the feedback offset steps are a small amount of the received signal.

I don't see what the problem is visualizing this.

This stuff is old news you don't see it in IEEE JSSC
publications, because its been around so long.

Title: Re: DC offset cancellation
Post by RobG on Apr 24^th, 2012, 2:48pm

loose-electron wrote on Apr 24^th, 2012, 2:29pm:

Like I said - you can also do it in a continuous mode ,
as long as the feedback offset steps are a small amount of the received signal.

Well duh, even I can see that ;) But won't that put a 1 lsb tone at the update frequency?

Title: Re: DC offset cancellation
Post by loose-electron on May 5^th, 2012, 10:46am

sure will, but that can be dealt with, and you have a lot of freedom in how you control your feedback updates.