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Design >> Mixed-Signal Design >> Clock generator for latched comparator
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Message started by gsensor on Apr 24^th, 2012, 2:40pm

Title: Clock generator for latched comparator
Post by gsensor on Apr 24^th, 2012, 2:40pm

Hi guys,

I'm currently designing a latched comparator working with a 200 MHz ideal clock in Spectre Simulator with CMOSP13 IBM technology. I don't know if its best to implement this 200 MHz clock on-chip or to have an output signal linked to an off-chip clock generator. As I have no experienced with circuit working with a clock, I don't know which option is best in terms of precision ? My guess is going with an on-chip clock, but which topology, taking in consideration low complexity and low space ? A VCO, or do I need a PLL for this frequency ?

Thanks for your help,
gsensor

Title: Re: Clock generator for latched comparator
Post by carlgrace on May 11^th, 2012, 1:27pm

The answer to this really depends on your specs. An off-chip clock that you buffer on-chip is MUCH, MUCH, MUCH simpler than implementing a PLL. So your decision should be like this:

1. Can I make an off-chip clock work? Why not? Can I address any of the reasons why not in a simple way?

2. I have no choice, I will need a PLL.

The thing is, if you have an on-chip clock generator, you will potentially have much better jitter performance (and programmablility) but you'll STILL need an off-chip clock for a reference.

Title: Re: Clock generator for latched comparator
Post by loose-electron on May 24^th, 2012, 1:33pm

external clock if available elsewhere in your system, probably crystal generated.

Take whatever the available frequency is and divide it down inside your design to the desired frequency.

Things like RC oscillators etc are not very accurate.