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Design >> Analog Design >> Output swing of CML buffer
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Message started by Yutao Liu on May 6^th, 2012, 2:46am

Title: Output swing of CML buffer
Post by Yutao Liu on May 6^th, 2012, 2:46am

Hello everyone,
I am designing a CML buffer, whose input frequency is up to 5GHz, and its output load is modeled by a 300fF capacitor. It is driven by a LC-tank VCO.
In the schematic simulation, the output swing is above 400mV. However, the output swing is only 240mV in the post-layout simulation. I ran DC simulation and found that there was about 170fF parasitic capacitor on the input line and 60fF on the output line. I suspect that only a little parasitic capacitor can decrease the output swing so much.
Does the parasitic capacitor cause significant difference? Or something else? Could you give me some advice?

Thanks,
Yutao

Title: Re: Output swing of CML buffer
Post by raja.cedt on May 6^th, 2012, 4:56am

hello,
in principle a capacitor can't change CML driver swing. But it can reduce the BW of the driver and may be your differential pair is not switching completely.reduce the frequency of the VCO And check the swing. POST THE RESULTS

Title: Re: Output swing of CML buffer
Post by Yutao Liu on May 9^th, 2012, 7:43am

Hello reja,
The results show as follow,
Input frequency = 5000MHz, CML buffer output swing is 364mV for schematic simulation, and 178mV for post-layout simulation.
Input frequency = 4050MHz, CML buffer output swing is 590mV for schematic simulation, and 309mV for post-layout simulation.

According to the results above, I agree with that the parasitic capacitor reduces the BW of the buffer. So, increasing bias current and reducing load resistor is the way to enlarge the output swing, isn't it? It seems power consuming. If the input frequency covers a wide frequency range, the buffer waste power when working on lower frequency. Is there any better approach?

By the way, I used to think that limited BW cause incomplete switching in differential pair. What is the difference between them?

Thanks for your help.
Yutao

Title: Re: Output swing of CML buffer
Post by raja.cedt on May 9^th, 2012, 10:03am

hello man,
buffer design is not good man...whats your swing (i mean whats the total bias current and whats the load resister then I*R) and apply very low frequency signal and check the swing. And then do a ac simulation to get the BW. I guess your BW is below 4G. Please post your schematic. I would suggest you to go for cascode driver still if you need more BW go for neutralization.

Incomplete switching means you get less swing and is same for all frequencies, where as less BW means for low frequency you get correct swing.

Increasing current doesn't increase BW, so decreasing resister does but to maintain swing you need to increase current.
refer razaavi text book on optical communications for more details...

Thanks,
Raj.