The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> RF Design >> question on double extraction issue in RF mos
https://designers-guide.org/forum/YaBB.pl?num=1336621374

Message started by snaildr on May 9^th, 2012, 8:42pm

Title: question on double extraction issue in RF mos
Post by snaildr on May 9^th, 2012, 8:42pm

Hi all

I'm a student new to circuits. Recently I've been working on a CMOS tapeout using a tsmc RF CMOS process and ran into an issue with the foundry RF MOSFETs. After spending some time debugging I'm still puzzled. I'd really appreciate your input. I currently left some of the numbers in this posting as "X" for confidentiality reasons, but I'd love to share them and also some screenshots via PM, if you have the access to the PDK.

I was trying to design a traveling-wave amplifier, using foundry RF mosfet and HFSS simulated transmission lines. I found that post-layout simulation showed significant bandwidth degradation compared to schematic simulation (BW dropped from 71GHz to 46GHz). I was able to locate that the main problem is the parasitics from the RF mos (nmos_rf), because when I did a "skeleton" extraction by keeping everything in the layout but the nmos_rf, the bandwidth reached 64GHz.

Then I did ft simulations on the nmos_rf that I was using. The setup is just a two port S-parameter simulation of the mos with (gate, gnd!) being port1 and (drain, gnd!) being port2, and watch the H21 crossing 0dB to get ft. In schematic simulation I got ft= X GHz. Then I created the corresponding layout by using one nmos_rf layout from the library and placed pins for the 4 terminals (the pins are on "pin" purpose layer so they shouldn't create actual shapes). Post-layout simulation was done by both Assura QRC (RC mode) and Calibre PEX (R+C+CC mode), the resulting H21 curves from Assura and Calibre almost overlap exactly. But they are very different from the H21 obtained from schematics simulation, and the ft now is only 0.73*X. Similar thing for fmax, but in the fmax case Calibre generates more pessimistic result than Assura. When I opened the av_extracted view or the calibre view, I saw parasitic resistors and capacitors inside the nmos layout region (on the fingers, on the guard ring, everywhere).

I was under the impression that the foundry builds RF mos models specifically for these nmos_rf, so that Assura and Calibre shouldn't go into the cell to do extraction, right? During schematic simulation I certainly saw the RF model elements such as the gate resistance rgx and metal capacitance cgs_m, cgd_m etc being calculated correctly compared to what I get based on the RF model manual. I think these elements are being used too, because if I replace RF mos with non-RF mos I got significantly better results. So, it seems to me Assura and Calibre are doing double-extraction, do you know how to fix this?

thanks a lot,
Ran

Title: Re: question on double extraction issue in RF mos
Post by ACWWong on May 18^th, 2012, 10:02pm

yes double extraction is always a worry. often it is handled by either:
1) CAD layers in the kit which tell Assura/Calibre where not to extract.
2) If you do extract, you switch to nominal non-RF device model.

For transistors (1) is more common, but I'm not a tsmc user so can;t comment on their flow.

Title: Re: question on double extraction issue in RF mos
Post by snaildr on May 19^th, 2012, 12:55am

Hi ACWWong

Thanks for the reply. For (1), yeah, I see layers for RF mos recognition presented in the cell, it is essential for LVS but doesn't seem to work in the way it's suppose to during parasitics extraction which causes the double extraction problem.

For (2), it is the way I had to take for the current tapeout, it's non-ideal because there are things like noise you couldn't account for by extraction on regular devices. BW might be largely right though.

Ran