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Design >> Analog Design >> latch metastability and delay time
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Message started by medya on May 11^th, 2012, 1:14pm

Title: latch metastability and delay time
Post by medya on May 11^th, 2012, 1:14pm

Hi everyone
I need to know how simulate a latch(back to back inverter)that will be used in comparator structure.when I run tran analysis due to multiple dc operation point(metastable)even i use IC in spectre the output voltage dont settle to stable points.can any one tell me how to simulate or give comments about make a right test bench?i search and see many book and articles but they dont say the detail of simulation. :-/last of them was CMOS Circuit Design, Layout, and Simulation >>Chapter 13 Clocked Circuits>>p384
thanks.