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Design >> RF Design >> Intuitive analysis of LNA
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Message started by kollayliu on May 14^th, 2012, 1:59am

Title: Intuitive analysis of LNA
Post by kollayliu on May 14^th, 2012, 1:59am

Inductive degeneration LNA with and without an extra Cgs are two commonly used LNA configuration.

Both of inductive degeneration and an extra Cgs considerably affect the channel noise and induced gate noise, Compared to simple single MOSFET, it's more difficult to intuitively analyze these two techinques' effect on the two noise sources.

I want to find an intuitive analyzing way which can give me much insights. Basically, my question is: To what level source degeneration and extra Cgs can improve or degrade the noise performances, and why?

What are your guys' clever and intuitive analyzing way?

Thank you.

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Title: Re: Intuitive analysis of LNA
Post by aaron_do on May 14^th, 2012, 7:46am

Hi,

I haven't looked at this in a while, so somebody else will probably give a better answer, but intuitively, adding a Cgs lowers the fT of the transistor. Therefore, the minimum possible noise figure is increased. However, as I understand it, it is then possible to achieve nearly simultaneous noise and impedance matching. So you get noise matching, but you are matching to a higher Fmin. (correct me if i'm wrong here)

regards,
Aaron

Title: Re: Intuitive analysis of LNA
Post by RFICDUDE on May 14^th, 2012, 5:44pm

It is somewhat difficult to obtain simple insight into the problem because there are several parameters and outputs (gain, NF, match, isolation, linearity, etc.).

But here is my input (for what it is worth).

The purpose of inductive feedback is to provide a degree of freedom in controlling the real part of the impedance at the gate without degrading NFmin (at least not degrading it much). Without this degree of freedom it would be more difficult to achieve a low NF for a CS amplifier because you would essentially noise match to the thermal resistance of the gate. This resistance is small, so the Q of the match would be large and the bandwidth small.

By using Ls, the real part of the impedance at the gate is
(gm x Ls) / Cgs and this can be related (approximately) to ft as Ls x ωt

Now if the ft of the MOSFET in the LNA design is very high then the degeneration inductance needs to be very large to produce a desired series resistance at the input. The degeneration obviously impacts the gain and therefore will increase the input referred noise resulting in increased NF. Lowering the ft of the MOSFET by adding extra gate cap will lower ft and permit the use of a smaller Ls to achieve a desired resistance at the gate.

As Aaron points out, the concern with adding Cgs is that the lower ft may increase the input referred noise of the CS stage causing a larger NFmin.

So, the result is that you can design your amplifier without the extra Cgs cap and see what value of Ls you need to achieve a desired real part to the gate impedance. If that Ls is so large that it prevents you from achieving your gain target then you can see if adding Cgs lowers the needed value of Ls and see if there is an increase in gain. If so, then adding Cgs is good trade-off towards meeting your design goals.

The above discussion is somewhat specific to cascode CS amplifiers with inductive degeneration. This is an important assumption as a straight CS amplifier has additional complications because of the limited isolation between the drain and gate circuits.

Hope the idea is clear.