The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> RF Simulators >> Simulating the effect of phase noise
https://designers-guide.org/forum/YaBB.pl?num=1337931696

Message started by manohar.b.n on May 25^th, 2012, 12:41am

Title: Simulating the effect of phase noise
Post by manohar.b.n on May 25^th, 2012, 12:41am

Hi all,
I want to study the effect of phase noise on my circuit performance. Is there a way I could create a source (signal generator) where I can give the phase noise number I want and then use it for simulation? Any helpful pointers would be greatly appreciated.

Manohar

Title: Re: Simulating the effect of phase noise
Post by ACWWong on Jun 7^th, 2012, 9:27am

Assuming you are using Cadence, then there is a library as part of the installation called rfLib. Inside there there is a cell called vco which is a verilogA model of what you want.

Other options are to write your own model. You can get ideas on this website:

http://www.designers-guide.org/VerilogAMS/functional-blocks/vco/vco.va