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Design >> Analog Design >> Can I design a hysteresis comparator which is used in integration ADC like this?
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Message started by chaojixin on May 29^th, 2012, 2:29am

Title: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by chaojixin on May 29^th, 2012, 2:29am

I set the W/L of M2 larger than M6 to make the hysteresis curve different from the common comparator.
but I use this comparator in integration ADC which Vi1 connect to a DC level and Vi2 to a ramp wave. Vi1 never near the start point of ramp wave.
Can I design the comparator like this in my case? what's the problem of it?

thanks!

Title: Re: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by loose-electron on May 30^th, 2012, 1:12am

Integration ADC have mostly stop being used.
Consider a sigma-delta method, or a VCO counter structure.

As a method to introduce hysteresis, the method and architecture will work, although there are other methods also.

Title: Re: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by chaojixin on May 30^th, 2012, 3:40am

but in fact it is not a real 'hysteresis'. the real 'hysteresis' is like this. so I'm afraid such a comparator will be sensitive to noise

Title: Re: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by loose-electron on Jun 3^rd, 2012, 2:55pm

the circuit shown will give the desired hysterisis effect, when the sizes of the devices are widely mismatched.

The original drawing of the response is incorrect, and the newer one is accurate, agreed.

Title: Re: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by chaojixin on Jun 4^th, 2012, 8:41pm

both drawing is correct. the curve in original drawing is made by setting W/L of M3 larger than M6 , and the newer one (ordinary case which has real hysteresis) is made by setting W/L of M3 smaller than M6.
my question is, does the comparator in original drawing has any drawback?

Title: Re: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by loose-electron on Jun 10^th, 2012, 1:15pm

chaojixin wrote on Jun 4^th, 2012, 8:41pm:

It is only the inpput stage to a comparator.

You will probably need a second gain stage and an output buffer

Title: Re: Can I design a hysteresis comparator which is used in integration ADC like this?
Post by pf66 on Aug 13^th, 2012, 7:01am

Dear Chaojixin,

Your hysteresis plot will be sensitive to mismatch of M2/M6. Moreover, they are NMOS/PMOS and can not really be matched.

Any special reason why not use high gain two-stage (with possible offset compensation/auto zero at first stage) ?

Alex