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Design >> RF Design >> different types of tiedown rules are very confusing
https://designers-guide.org/forum/YaBB.pl?num=1338412194

Message started by peterki on May 30^th, 2012, 2:09pm

Title: different types of tiedown rules are very confusing
Post by peterki on May 30^th, 2012, 2:09pm

Hi there is an excellent discussion on tiedown diodes in
http://www.designers-guide.org/Forum/YaBB.pl?num=1141663850/1#1.

:)

However, I can't find the information I needed in that discussion. There are a number of tie down rules in IBM 130 nm process.

1. why n-well needs to be tied down? I know the gate needs tie-down because the thin oxide might be damaged. However I don't understand why n-well needs tie down.

2. what is pTiedown meant for? a pTiedown is p+ diffusion to n-well. However in fabrication, n-well is not connected to any voltage.

3. how p-mos gate is protected? what tiedown diode should be used?

I really appreciate anyone can share some experience on this topic.

Title: Re: different types of tiedown rules are very confusing
Post by loose-electron on Jun 3^rd, 2012, 2:51pm

1. why n-well needs to be tied down? I know the gate needs tie-down because the thin oxide might be damaged. However I don't understand why n-well needs tie down.

2. what is pTiedown meant for? a pTiedown is p+ diffusion to n-well. However in fabrication, n-well is not connected to any voltage.

3. how p-mos gate is protected? what tiedown diode should be used?

You are trying to control the voltage of what is on top of the gate oxide (the gate itself) and whats under the gate oxide (namely the n-well bulk under PMOS transistors, or simply the substrate bulk under the NMOS transistor)

Adding to the confusion on antenna effects and similar - sometime there are tie downs specificed for situations that happen during the foundry process and certain fabrication layers are not yet in place.

Title: Re: different types of tiedown rules are very confusing
Post by peterki on Jun 3^rd, 2012, 5:06pm

thanks for the reply.

My guess is that it is important to control the voltage of n-well during fabrication. The tie-down diode is a leakage path for n-well. In case too much voltage is incurred, the tie-down diode releases the charges, to protect the pmos gate oxide.

loose-electron wrote on Jun 3^rd, 2012, 2:51pm:

Title: Re: different types of tiedown rules are very confusing
Post by loose-electron on Jun 5^th, 2012, 9:45pm

thats not a guess, that is actually correct.

I was part of IBM's semiconductors group at a design center out here in San Diego and was very involved
in creating the CMOS RF processes and several of the SiGe processes.

Their semiconductor modeling is pretty good quality.

Title: Re: different types of tiedown rules are very confusing
Post by peterki on Jun 6^th, 2012, 7:10am

Thanks a lot for sharing your industry experience.

Now I know how to protect nmos gate (N+/sub contact), pmos N-well (N+/sub contact outside of the n-well). This also goes to MIM capacitor. Diode protection is required in MIM.

I am wondering if it is necessary to protect the pmos gate using tieDown diode. What diode should be used to do so?

loose-electron wrote on Jun 5^th, 2012, 9:45pm:

Title: Re: different types of tiedown rules are very confusing
Post by loose-electron on Jun 10^th, 2012, 1:11pm

peterki wrote on Jun 6^th, 2012, 7:10am:

If it is not on the foundry provided design rules you don't need to do it. Frequently there are lithography steps that will deal with things that you are not directly defining.

If they don't request PMOS gate ties (which would be to the N-well to control gate to bulk potential) you do not need it.