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Simulators >> Circuit Simulators >> Do the corner of different devices in tsmc has some relationship
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Message started by easyads on Jun 11^th, 2012, 2:35am

Title: Do the corner of different devices in tsmc has some relationship
Post by easyads on Jun 11^th, 2012, 2:35am

Hi ,all
The following question is about tsmc 0.13um RF process
1. Do the corner of core device and IO device has some relationship? For example, if nmos1v goes to "tt" corner, then nmos3v will also go to "tt" corner? Or the nmos1v and nmos3v's corner has no correlation?
2. Please describe the corner relationship between mos_var and core device "nmos1v, pmos1v". For example, if nmos1v goes to "ss" corner, then mos_var will also go to "ss" corner ?
3.Please describe the corner relationship between bjt devices "vpnp, npn" and core device "nmos1v, pmos1v". For example, if nmos1v goes to "ss" corner, then vpnp will also go to "ss" corner ?
4. Please describe the corner relationship between diode devices "diodep,dioden" and core device "nmos1v, pmos1v". For example, if nmos1v goes to "ss" corner, then diodep will also go to "ss" corner ?
5. Please describe the corner relationship between rphpoly and rphriply; between rphpoly and rnhpoly; between rphpoly and rplpoly. For example, if rphpoly goes to "ss" corner, then rphripoly will also go to "ss" corner ?

Thank you.

Title: Re: Do the corner of different devices in tsmc has some relationship
Post by Geoffrey_Coram on Jun 11^th, 2012, 5:32am

I'm not sure anyone on this forum can answer your specific questions without violating non-disclosure agreements. Your best bet would be to contact your foundry representative.

That said, I can give you some starting points based on simple concepts. One gets correlations of devices when they share processing steps: core NMOS and PMOS will have a correlation from the oxide thickness, but not from their threshold voltage implant. 1V and 3V devices probably have different oxide thicknesses, so they would not be correlated from that. However, all MOS devices (including mod_var) will likely have correlations from the over/under-etch (delta-W, delta-L).

Beyond that, you'll have to ask the foundry rep, or carefully study the process documents you have: does the vpnp share any processing steps with nmos1v? Are the n or p implants of one device created the same way as the other?

Since the devices won't share every processing step, though, there won't be perfect correlation for any two device types. It may be difficult, also, to know how much of the variation in a particular device is due to a processing step that is shared with another, and how much is due to other steps.

Title: Re: Do the corner of different devices in tsmc has some relationship
Post by Kevin Aylward on Jul 7^th, 2013, 4:17am

Irrespective of the physics, its highly unlikely, imo, that the fab kits will have any devices of same type tracked differently. All nmos types will be made “fast” together, all resisters will be “fast” together. You can check by simply going and looking at the model files! On a similar note, they semi pick out of the air how much they are varied. It is always fixed round numbers like +/-10%, +/- 20% for res and cap, +/0.1V for Vt etc. In fact some fabs are as dubious as only providing a kit with bipolar npns and pnps tracked together, which makes them useless as is. Manual files and broken kits is then the norm. Apparently, fabs don’t care much for BiCMOS, even when they offer such processes.

Title: Re: Do the corner of different devices in tsmc has some relationship
Post by tm123 on Jul 22^nd, 2013, 11:59am

easyads,

My experience is very similar to what Kevin has outlined. Models will show devices tracking over process corners when in real life that is never the case. You can learn a lot about this by reading the actual model files even though they can seem cryptic at first. Especially for resistors, many fabs control the variation much more closely than what models predict. For example, if you simulate +/-20% process variation of a resistor you may see 10% in real life across many wafers.

Since you are at the mercy of the fast/slow corners for process simulation, you can try a process Monte Carlo sim and see if you get different results.

Hope this helps.

Tim