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Design >> Analog Design >> Problem on SCL Latch in 40nm technology
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Message started by Yutao Liu on Jun 15^th, 2012, 7:11am

Title: Problem on SCL Latch in 40nm technology
Post by Yutao Liu on Jun 15^th, 2012, 7:11am

Hello everyone,
I am designing a divided-by-2 with SCL latch by 40nm low power technology. The supply voltage of the circuitry is limited to 1.1V, and the threshold voltage of transistor is about 0.6V. As shown in simulation result in figure 2, there is a significant spike in the latch output waveform.
In my opinion, the NMOS as tail current source is biased at triode region so that the ripple at node Y is large. The ripple causes incomplete switch of the clock-driven differential pair. As a result, the input differential pair still amplifier input signal even when the clock is supposed to shut them down.
My questions are,
1. Is my analysis right?

2. The circuity topology is three NMOS in stack. It is difficult to bias this circuit with the limited supply voltage and large threshold voltage. Can I abandon the tail current source to get an easier bias? It there any suitable topology?

3. Can my circuit be further optimized? It seems useless to adjust parameters in the circuit.

Thanks in advanced,
Yutao

Title: Re: Problem on SCL Latch in 40nm technology
Post by Yutao Liu on Jun 15^th, 2012, 7:14am

Figuire2 is shown as following.

Title: Re: Problem on SCL Latch in 40nm technology
Post by loose-electron on Jun 15^th, 2012, 9:52am

Yutao Liu wrote on Jun 15^th, 2012, 7:11am:

2. The circuity topology is three NMOS in stack. It is difficult to bias this circuit with the limited supply voltage and large threshold voltage. Can I abandon the tail current source to get an easier bias? It there any suitable topology?

Try using a resistor instead of the current source.

Title: Re: Problem on SCL Latch in 40nm technology
Post by Yutao Liu on Jun 16^th, 2012, 1:03am

Thanks Jerry, I will try your idea.
Could you tell me why resistor as tail current source is your option.
I think the resistor would display the same characteristic as an NMOS in triode region. The ripple at node Y still exist. Do I miss anything?

Best,
Yutao

Title: Re: Problem on SCL Latch in 40nm technology
Post by Yutao Liu on Jul 2^nd, 2012, 7:44am

loose-electron wrote on Jun 15^th, 2012, 9:52am:

Yutao Liu wrote on Jun 15^th, 2012, 7:11am:

Try using a resistor instead of the current source.

The spike does exist with resistor, and the amplitude is the same as that with current source. But the swing(Vmax-Vmin) becomes larger.

I checked the circuit again and found that there is about 160uA gate leakage current in the clock-driven differential pair. I think this leakage also causes the spike, doesn't it?

Thanks,
Yutao Liu

Title: Re: Problem on SCL Latch in 40nm technology
Post by Lex on Jul 4^th, 2012, 12:38am

You say that the threshold is 0.6 V? So why biasing the current source at 535.6 mV? I guess it should be at least 0.7 V?

Title: Re: Problem on SCL Latch in 40nm technology
Post by Yutao Liu on Jul 6^th, 2012, 7:46pm

Lex wrote on Jul 4^th, 2012, 12:38am:

You say that the threshold is 0.6 V? So why biasing the current source at 535.6 mV? I guess it should be at least 0.7 V?

The threshold is 0.6V when the length of FET is 40nm. And the threshold voltage decreases when length increases. In the schematic attached, the length of current source is above 40nm. So its bias voltage is lower than 0.6V.

Best,
Yutao

Title: Re: Problem on SCL Latch in 40nm technology
Post by Lex on Jul 9^th, 2012, 12:59am

Okay that makes sense.

Did you try optimizing the common mode level of the clock? Are you certain the coupling cap is large enough? Can't see any sizes on the schematic, but I assume you thought about it.