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Design >> Analog Design >> Possible ESD weaknes in circuit ??
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Message started by ic_engr on Jun 19^th, 2012, 9:36am

Title: Possible ESD weaknes in circuit ??
Post by ic_engr on Jun 19^th, 2012, 9:36am

Hello,

One of our designers designed a resistor using PMOS transisotrs such that the last PMOS source is connected to VSS, the drain and bulk are connected to some other potential level.

In attached picture it is the device M12 PMOS. The question is whether this design would cause any potential ESD failures by virtue of having PMOS source to VSS ? The design is in 0.18um technology.

This is no different when in regulators, the output PMOS source is conected to a PAD, and the bulk and drains are also connected to VBAT, and we rung ESD test on regulator output pin.

Regards

ic_engr

Title: Re: Possible ESD weaknes in circuit ??
Post by ic_engr on Jun 19^th, 2012, 9:37am

Sorry reword, the PMOS DRAIn is connected to VSSA and not Source. So are we risking any ESD complaince.

ic_engr

Title: Re: Possible ESD weaknes in circuit ??
Post by loose-electron on Jun 22^nd, 2012, 4:09pm

In an ESD strike how high can the bulk go above ground or below ground?

Thats the big question. Gate is at ground, and gate to bulk voltage is what will fry the oxide.

Do not know what the ESD circuits are attached elsewhere.

Title: Re: Possible ESD weaknes in circuit ??
Post by ywguo on Jun 27^th, 2012, 6:52am

Hi ic_engr,

I do not know much about ESD as a circuit designer. In the circuit level, you need ESD protection device to protect your circuit. When there is an ESD strike according to your specification, the ESD protection device discharges the charge and limits the maximum voltage accross your circuit. So Jerry said, "Do not know what the ESD circuits are attached elsewhere."

Best Regards,
Yawei