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Design >> Analog Design >> Second-Stage Folded Cascode amplifier CMOS ?
https://designers-guide.org/forum/YaBB.pl?num=1340245797

Message started by gsensor on Jun 20^th, 2012, 7:29pm

Title: Second-Stage Folded Cascode amplifier CMOS ?
Post by gsensor on Jun 20^th, 2012, 7:29pm

Hi,

I'm working with 0.13 um CMOS (IBM) technology with a 2.5V supply.
I have designed successfully a one-stage folded cascode amplifier, providing low noise and low power by using large length device for cascode mirrors. This op-amp as the following characteristics:

Open-loop gain: 75 dB
PSSR+: 80 dB
PSSR-: 75 dB
Output swing: 0.4V-2.1V (Gnd+Vth ,Vdd-Vth)
Input voltage: 0.3V-1.25V (I will use this op-amp only with this range of input vcm..)
Power: 32 uW
Bandwidth: 3 kHz (limited by C load)
C load=2pF

As I need a rail-to-rail output swing, low power dissipation, a bandwidth of 4 kHz and an open-loop gain of at least 80 dB, I have tried, unsuccessfully to add a second stage to this op-amp, using a simple indirect feedback compensation (see below).

The problem is that I keep getting a huge offset no matter how I size the 2 transistors of this second stage....What I'm I doing wrong ? Is there a proper way to design this stage ?

If this is not possible with my specifications, what other second stage could provide me the rail-to-rail output swing I'm seeking, without an offset voltage bigger than 200 uV (without mismatch variations) for an input common voltage of 0.3V to 1.2V and without increasing dramatically power consumption ?

Thanks a lot for your help !
gsensor

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by gsensor on Jun 20^th, 2012, 7:50pm

The devices operating points appearing on the image are obtained with the open loop gain test.

W/L:

T3-T4: 6.5u/30u
T5-T9:10u/1u
T1-T0: 2u/20u
T20-T10: 23u/60u
T59 and T65 ?

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by Lex on Jun 21^st, 2012, 12:33am

Vds of the T65 is quite low, feedback configuration not shown, so difficult to conclude why (at least, for me ;)).

And to be honest, 200 uV static offset is probably way below the mismatch variation.

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by gsensor on Jun 21^st, 2012, 12:21pm

Hi Lex,

thanks for your response.
When I simulate the offset voltage, either T3-T4 and T5-T9, or T0-T1 and T10-T20 is off or in triode region, depending of the vcm I use. I can size T59 and T65 to a way that they are both in saturation and offset voltage is minimized, but it only works for a specific vcm input, let's say 400 mV. If I use vcm=1V I still get that huge offset..

For mismatch, I meant, 200 uV without considering mismatch variations in simulations..

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by Lex on Jun 22^nd, 2012, 12:59am

If that is the case, that means you don't have a bias loop, meaning you're probably simulating open loop? Frankly speaking, I think the problem is related to your test bench.

Anyhow I don't see much wrong with this circuit. Sure there are ways to improve (e.g. cascoding 2nd stage to reduce early effect), but not much to win imho.

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by gsensor on Jun 22^nd, 2012, 10:03am

I test the voltage offset in a close loop configuration (voltage follower) : Vin+ = Vcm and Vin-= Vout.

The image attached shows the transistors operating in that configuration, for an input voltage of 0.3 V (Vcm=0.3V)...To which I get a huge offset of 2.18V. In open-loop configuration, every transistors, including T59 and T65 are in saturation. Althougth, I also have a phase starting at +150 degrees ?
T59=5u/60u and T65=(2.7*5u)/60u

Could you give me some guidelines on how to set the size of the second-stage transistors ? Is the problem caused by the first-stage ?

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by wave on Jun 22^nd, 2012, 12:47pm

Clearly you are NOT in saturation on T58, T59, T7.
Your VDS are collapsing due to PFB.
Try swapping +/- inputs.
Also your + input is 1V not 0.3 as you state.

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by gsensor on Jun 22^nd, 2012, 2:25pm

Right, Vcm= 1V on the schematic shown, sorry for that.

I have swap + and - inputs, and my problem is solved! No more huge offset!..I had tried everything, without considering that my circuit configuration might have been the problem...hughh
Thanks wave !!!

Title: Re: Second-Stage Folded Cascode amplifier CMOS ?
Post by Lex on Jun 26^th, 2012, 12:27am

Well spotted wave! =)