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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Extracting gate resistance value in cadence https://designers-guide.org/forum/YaBB.pl?num=1341854869 Message started by nadroit on Jul 9th, 2012, 10:27am |
Title: Extracting gate resistance value in cadence Post by nadroit on Jul 9th, 2012, 10:27am Hello All, I am trying to simulate/extract gate resistance of nmos device (IBM 90nm). technology uses BSIM4 model which models gate resistance in two components namely intrinsic input impedance (Rii,bias dependent) and polysilicon gate resistance. 1. I am measuring S parameters of the device with Spectre by doing .sp analysis (figure attached,set up shown for BJT but it is same for MOS) 2. Spectre gives Y parameters and Real{Y11}=w^2*Cgg^2*Rg. Thus Rg can be extracted.[Ref http://www.silvaco.com/tech_lib_TCAD/simulationstandard/2000/jan/a1/a1.html] 3. BSIM4 literature suggests that Rg decreses as Vgs increases but I am observing opposite results. I am not sure what mistake I am making. is my setup correct? Please let me know if you have any other method of extracting gate resistance. Also output parameters of spectre gives value of rgbi and rgbd, spectre manual lists both of them as gate bias dependent resistor. But I am not sure what it is,is it the gate resistance?? As you can see I am very confused please help. Thanks |
Title: Re: Extracting gate resistance value in cadence Post by loose-electron on Jul 13th, 2012, 4:24pm The resistance of the gate may not be in the model. Frequently the parameter may be in the transistor model (BSIMX.X), but the foundry's model implementation (IBM's 90nm NMOS model done using the BSIMX.X model) may not have the value set. Value not set and it defaults. Default value for gate resistance is 0. You can approximate the gate resistance by finding the ohms/square for the silicided polysilicon layer that the gate is made out of and use that to get the resistance. |
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