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Design >> Analog Design >> regulator & PLL/DLL transfer function or bandwidth
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Message started by casual on Jul 9^th, 2012, 7:26pm

Title: regulator & PLL/DLL transfer function or bandwidth
Post by casual on Jul 9^th, 2012, 7:26pm

hi

If the PLL/DLL close-loop bandwidth is 5MHz, does it mandate a wideband voltage regulator (good PSRR for wideband). Could the voltage regulator PSRR freq be relaxed since the PLL/DLL loop bandwidth is 5MHz.

Title: Re: regulator & PLL/DLL transfer function or bandwidth
Post by casual on Jul 17^th, 2012, 12:53am

hmm.. the power noise transfer function in PLL/DLL is high-pass. can i say that it requires voltage regulator with good PSRR for wideband freq?

Title: Re: regulator & PLL/DLL transfer function or bandwidth
Post by BackerShu on Jul 18^th, 2012, 8:55pm

Not exactly, for regulating VCO in a PLL/DLL, TF from regulator input to output, and TF from regulator output to VCO output (usually it's a bandpass TF) should be considered together. Usually, an optimal design would achieved by misaligning peaks of two TFs.

These two papers would be good references for this:
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5173751&tag=1
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5518351

Title: Re: regulator & PLL/DLL transfer function or bandwidth
Post by casual on Jul 18^th, 2012, 10:24pm

thank you very much
i will take a look on these papers