The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> simulating synthesized verilog digital unit with analog unit
https://designers-guide.org/forum/YaBB.pl?num=1341955241

Message started by mohammadreza on Jul 10^th, 2012, 2:20pm

Title: simulating synthesized verilog digital unit with analog unit
Post by mohammadreza on Jul 10^th, 2012, 2:20pm

Hi! I am doing a mixed-signal design using a control unit for my analoge part. I wrote it in VHDL in modelsim and then synthesized it using Encounter and AMS C35 library file and checked the post synthesis verilog code in Modelsim and it passed the test bench.

Now I want to use it beside my analoge unit. I created a cell view for it and chose verilog editor and functional as the cell view. Now when running the simulation it gives me an error that the instance in the library with cell view functional is not found?

Could you please help me what I should exactly do to be able to run this verilog generated cell in my analoge design?

Thanks

Title: Re: simulating synthesized verilog digital unit with analog unit
Post by carlgrace on Jul 11^th, 2012, 6:16pm

It depends entirely on your tool flow. Can you make sure it compiled the functional view correctly?