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Design Languages >> Verilog-AMS >> I(<vin>) and I(vin,vin)
https://designers-guide.org/forum/YaBB.pl?num=1342145317

Message started by ywguo on Jul 12^th, 2012, 7:08pm

Title: I(<vin>) and I(vin,vin)
Post by ywguo on Jul 12^th, 2012, 7:08pm

Hi Guys,

I see the following code in a verilogams model. What does it mean with I(<vin>) and I(vin,vin)?

`ifdef __VAMS_ENABLE__
iin_val = I(<vin>);
`else
iin_val = I(vin,vin);
`endif

Best Regards,
Yawei

Title: Re: I(<vin>) and I(vin,vin)
Post by Ken Kundert on Jul 12^th, 2012, 9:02pm

I don't know what I(vin,vin) means, but I(<vin>) signifies a port current. Presumably I(vin,vin) means the same, and this model is written to operate on two different simulators that have different ways of representing port currents.

-Ken

Title: Re: I(<vin>) and I(vin,vin)
Post by boe on Jul 17^th, 2012, 9:05am

Yawei, Ken,

From V-AMS reference: "OVI Verilog-A 1.0 syntax for a current probe is I(a,a). OVI Verilog-AMS 2.0 changes this to I(<a>)."

The syntax given works for both.

- B O E

Title: Re: I(<vin>) and I(vin,vin)
Post by ywguo on Jul 17^th, 2012, 7:08pm

Hi Ken and B O E,

After read your posts, I find the description about probes in OVI Verilog-A LRM 1.0 and accellera Verilog-AMS LRM 2.3.1. It is clear now. Thank you very much.

Yawei