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Design >> Analog Design >> Extremely low power inverters
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Message started by mixed_signal on Jul 13^th, 2012, 9:29am

Title: Extremely low power inverters
Post by mixed_signal on Jul 13^th, 2012, 9:29am

Hi,
I am designing a buffer using a simple inverter at the o/p of a vco. The switching current should be<1uA since max available is 3uA. For this I have to size PMOS as 1u/40u and NMOS as 250n/40u. Will this extremely less w/l cause any problems? The supply is 1.2V.

The O/P has slight spikes at the transition points.

Title: Re: Extremely low power inverters
Post by boe on Jul 17^th, 2012, 9:13am

Mixed_signal,

L=40u? What is your load? f=?

- B O E

Title: Re: Extremely low power inverters
Post by mixed_signal on Jul 17^th, 2012, 10:09am

It is the O/P. I may feed it to FPGA for further processing so it has to go through level converters. Frequency is in khz i.e. 15khz

Title: Re: Extremely low power inverters
Post by boe on Jul 17^th, 2012, 12:05pm

Mixed_signal,
a few questions/hints:
Is your current requirement for I_peak or I_avg?
Is the transistor model realistic for L=40u?
Did you include the (external) load in your simulation?
What is the rise/fall time with ext. load? How does the load react to that?

- B O E

Title: Re: Extremely low power inverters
Post by mixed_signal on Jul 18^th, 2012, 1:14pm

Hi,
My current requirement is for peak current=3uA. My average current is 300nA.
I m not sure about the models. i m using ibm130cmrfsf8.

I did not add any external load in simulation.

Title: Re: Extremely low power inverters
Post by mixed_signal on Jul 18^th, 2012, 2:01pm

I will have a series of scaled inverters to match my load. Besides, I want to know how do you layout a 2u/40u device. Does fingering with 1u/40u make sense.
I have seen people in forums talking this issue for ultra low power circuits but with varied opinion. Some say to go for fingering , some say for length fingering or stacking and some ask not to go for such lengths!! :)