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Simulators >> RF Simulators >> pnoise analysis with verilog-A model frequency divider
https://designers-guide.org/forum/YaBB.pl?num=1342449029

Message started by dongbeidulang on Jul 16^th, 2012, 7:30am

Title: pnoise analysis with verilog-A model frequency divider
Post by dongbeidulang on Jul 16^th, 2012, 7:30am

Hi,

I add an ideal frequency divider in my pratical circuit with verilog-A model. I use the code from listing 3 in this paper Hidden State in SpectreRF http://www.designers-guide.org/analysis/hidden-state.pdf
It works for pss analysis. There is no hiden state problem. But for the pnoise analysis, there must be something wrong. Because the input of divider have phase noise about -110dBc at 20MHz, the output of divider shows no phase noise at all. It is only about -6.5kdBc.
Does anyone can explain this issue? Because I always expect that output will be noisy if the noisy input sigal passes an ideal frequency divider.

Please help me if you can.

Title: Re: pnoise analysis with verilog-A model frequency divider
Post by Frank Wiedmann on Jul 16^th, 2012, 3:26pm

See http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426.