The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Verilog A question
https://designers-guide.org/forum/YaBB.pl?num=1343165466

Message started by MarkG on Jul 24th, 2012, 2:31pm

Title: Verilog A question
Post by MarkG on Jul 24th, 2012, 2:31pm

I have a question about the Cadence library ahdlLib -> analog_mux,  the code is copied below.

Why do you need *BOTH* the following type of lines?

    selector = (V(vsel) > vth) ? 1: 0;

    @ (cross(V(vsel) - vth, 1, 1.0, vsel.potential.abstol))
        selector = 1;


won't the conditional operator (?:) , make it so that the selector value is always correct?  Or, do you need the @cross() so that you force the simulator to ALSO evaluate the value of "selector" at the crossings too (so that you get the value of selector changing at the correct time)?

code below:
---------------------------------------------------------------
module analog_mux(vin1, vin2, vsel, vout);
input vin1, vin2, vsel;
output vout;
electrical vin1, vin2, vsel, vout ;
parameter real vth  = 2.5;

  integer selector;
  real vout_val;

  analog begin
     selector = (V(vsel) > vth) ? 1: 0;

     @ (cross(V(vsel) - vth, 1, 1.0, vsel.potential.abstol))
        selector = 1;

     @ (cross(V(vsel) - vth, -1, 1.0, vsel.potential.abstol))
        selector = 0;

     if (selector == 1)begin
        vout_val = V(vin1);
     end
     else if (selector == 0)begin
        vout_val = V(vin2);
     end

     V(vout) <+ vout_val;
  end
endmodule


---------------------------------------------------------------


thanks
M

Title: Re: Verilog A question
Post by ywguo on Jul 25th, 2012, 1:48am

Hi MarkG,

@cross() is not evaluate at the initial time step. So the model gives X state until V(vsel) crosses vth for the first time unless selector is assigned using selector = (V(vsel) > vth) ? 1 : 0;

Another solution is replace @cross() with @above(), which is evaluate at the initial time step. Then the model needs not that conditional assignment.

Best Regards,
Yawei

Title: Re: Verilog A question
Post by Geoffrey_Coram on Jul 25th, 2012, 7:18am

cross() does also control the timestep so that the module is evaluated within timetol of a crossing.

The Designer's Guide Community Forum » Powered by YaBB 2.2.2!
YaBB © 2000-2008. All Rights Reserved.