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Design Languages >> Verilog-AMS >> Question about output current in VerilogAMS
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Message started by urian on Jul 24^th, 2012, 9:57pm

Title: Question about output current in VerilogAMS
Post by urian on Jul 24^th, 2012, 9:57pm

Hi,there
I have written a module in AMS, which output a current corresponding with the input binary code as follows:

Code:

module (Iout, Ain); //Iout is output current，and Ain is 2bits input.
output Iout;
input [0:1] Ain;
electrical Iout;
logic [0:1] Ain;

parameter real I = 6E-9; //unit current
real iout; //internal current variable；

always @(*) begin
case (Ain) //decide the iout from Ain
2'b00: begin iout = 5.0; end
2'b01: begin iout = 4.0; end
2'b11: begin iout = 3.0; end
2'b11: begin iout = 2.0; end
endcase
end

analog
I(Iout) <+ iout*I;//generating output current base on iout and I
end

When compiling the module, it gives a error message which shows that "I(Iout) <+ iout*I" has error with "illegal expression primary".
I dont know why and how to fix it, any suggestion will be appreciated.

Regards
urian

Title: Re: Question about output current in VerilogAMS
Post by ywguo on Jul 25^th, 2012, 1:57am

Your module has not any module name.

Please do NOT define parameter I because this is an access function for electrical node. Then the error message "illegal primary expression" disappears.

Best Regards,
Yawei

Title: Re: Question about output current in VerilogAMS
Post by urian on Jul 25^th, 2012, 8:45am

Thanks Yawei , you are right,the error has been fixed. Then what's the meaning of "illegal primary expression"?

Best regards
urian

Title: Re: Question about output current in VerilogAMS
Post by ywguo on Jul 25^th, 2012, 7:47pm

Hi urian,

In section 7.3.6.3, VerilogAMS LRM 2.3.1, it reads that an analog primary (variable, potential, or flow) whose value is ....
In section 7.3.6.5, VerilogAMS LRm 2.3.1, it reads that a digital primary (reg, wire, integer, etc.) whose value is ....

Obviously variable, potential and flow are primary in analog context, and reg, wire, integer, etc. are primary in analog context.

In your module, I is defined as a parameter. It results in illegal primary expression because I is access function of flow in verilogAMS.

Best Regards,
Yawei

Title: Re: Question about output current in VerilogAMS
Post by urian on Jul 25^th, 2012, 9:39pm

Thank you,Yawei ,I get it!
When I writting the module, I am confusing with the output current and voltage relationship.As in my module,there is only current output, then what about the port voltage?How does the module decide it?
When I using the module, I find that it makes the CMOS transistor which tied to it go into triode region.I wonder how to avoid it and accurate define the output relationship between current and voltage? Is it because my module is so simply?

Regards
urian

Title: Re: Question about output current in VerilogAMS
Post by Geoffrey_Coram on Jul 26^th, 2012, 5:35am

urian wrote on Jul 25^th, 2012, 9:39pm:

As in my module,there is only current output, then what about the port voltage?How does the module decide it?

From the Spice solver's point of view, you've defined an ideal current source. The module/current source doesn't decide the voltage; the solver applies the current and then tries to solve all the node voltages to satisfy Kirchoff's Current Law.

Title: Re: Question about output current in VerilogAMS
Post by urian on Jul 28^th, 2012, 3:49am

Hi,Geoffrey_Coram.So my module is just a ideal current source and its port voltage is determined by outside network.
And I find another problem.When I use "ground gnd" to declare a ground node and use it in "V(a,gnd)" statement, it said the gnd has not been declared.Is something wrong?

Regards
urian

Title: Re: Question about output current in VerilogAMS
Post by ywguo on Jul 31^st, 2012, 6:45pm

Hi urian,

Did you declare that gnd is electrical node? In Section 3.6.4, verilog-AMS LRM,

Quote:

Each ground declaration is associated with an already declared net of continuous discipline. The node associated
with the net will be the global reference node in the circuit. The net must be assigned a continuous
discipline to be declared ground.

Best Regards,
Yawei

Title: Re: Question about output current in VerilogAMS
Post by urian on Aug 1^st, 2012, 8:15am

Hi,ywguo, I did not declare the gnd as electrical node. I have seen in the book "THE DESIGNER’S GUIDE TO VERILOG-AMS", there is example code as below:

//A simple circuit
`include “disciplines.vams”
`include “vsrc.vams”
`include “resistor.vams”
module smpl_ckt;
electrical n;
ground gnd;
vsrc #(.dc(1)) V1(n, gnd);
resistor #(.r(1k)) R1(n, gnd);
endmodule

so I dont know it should be electrical. When refer to LRM, I have fixed this error as you said.Thanks a lot!

Regards
urian

Title: Re: Question about output current in VerilogAMS
Post by Ken Kundert on Aug 1^st, 2012, 10:28am

My mistake. Sorry about that.

-Ken