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Design >> Analog Design >> Comparator resolution 1.5bit/stage pipelined ADC
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Message started by medya on Aug 2^nd, 2012, 3:30am

Title: Comparator resolution 1.5bit/stage pipelined ADC
Post by medya on Aug 2^nd, 2012, 3:30am

Hi,
Assume that we design a pipelined ADC with 12bit resolution ,1.5bit/stage and vref=+/-1v,how the resolution of the comparators should be set?(in first stage), assume that the offset voltage is zero.

Title: Re: Comparator resolution 1.5bit/stage pipelined ADC
Post by BackerShu on Aug 2^nd, 2012, 10:20pm

First of all, assume whose offset voltage to be 0, opamp or comparator?

As to the comparator spec., at least the followings have to be met:

1. Speed. Assume conventional sturcture, about 0.5*Ts for comparator to give correct results. Make sure comparator meets this requirement in Worst Case condition and leave some margin based on your power budget.

2. Offset. For conventional 1.5b/Stage, the maximum offset can be tolerated is +/- 0.25*Vref; Yet, we usually don't go to this extreme. 250mV offset is really big, even in CMOS. 100mV may be more paratical. Again, how much margin you can have depends on how much power can be taken by comparators.

Title: Re: Comparator resolution 1.5bit/stage pipelined ADC
Post by medya on Aug 3^rd, 2012, 5:33am

thanks a lot BackerShu

Let me to ask my question in other form, assume we design a latched comparator, the settling time of the latch is ts=(cl/gm)*ln (vf/vin)(of course in simple form) my problem is that for truly operation if we have a few gain in preampilifier(the offset is zero!) for sizing of the latch by knowing the cl,vf,and ts we need to the vin value( this value set the minimum detectable signal by the latch ). what is this value for our design:1m,10m,100m????? :-?
in ohter words what is the resolution of the comparator 6bit,10 bit,12bit?????????????what is it :-/???
tell me a number!
best regards,
Medya.