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Design >> RF Design >> what is the current equation to be used for hand calculation in 65nm?
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Message started by elektra on Aug 13^th, 2012, 1:19am

Title: what is the current equation to be used for hand calculation in 65nm?
Post by elektra on Aug 13^th, 2012, 1:19am

I have to design CDR which operates at 5GBPS in 65nm UMC technology. What is the saturated current equation for hand calculations...Even if the answer lies 20% around the accurate value..its ok for me...

Title: Re: what is the current equation to be used for hand calculation in 65nm?
Post by AnilReddy on Aug 14^th, 2012, 5:41am

Hi,

You can simulate a transistor and find out the correction factor. What i mean is that if your transistors are not obeying the quadratic equation of the saturated current then you can find out the approximate "power" using this method. May be ~1.3 will be the power in those technologies but i am not sure...correct me if am wrong..

Thanks
Anil Reddy

Title: Re: what is the current equation to be used for hand calculation in 65nm?
Post by raja.cedt on Aug 14^th, 2012, 8:21am

use this pap

Alpha-Power Law MOSFET Model and its
Applications to CMOS Inverter Delay and
Other Formulas

Title: Re: what is the current equation to be used for hand calculation in 65nm?
Post by loose-electron on Sep 19^th, 2012, 7:42am

plot a set of bias curves for the transistors at a fixed geometry.

Use W/L scaling to get to the desired current.

Done.

Title: Re: what is the current equation to be used for hand calculation in 65nm?
Post by carlgrace on Nov 9^th, 2012, 10:02am

loose-electron wrote on Sep 19^th, 2012, 7:42am:

plot a set of bias curves for the transistors at a fixed geometry.

Use W/L scaling to get to the desired current.

Done.

Strongly agree with this. A bunch of hand calculation with square-law models will be a waste of time.

I'd suggest you look into the gm/I design methodology. It works really well with nanometer processes.