The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> instantiation inside analog block?
https://designers-guide.org/forum/YaBB.pl?num=1345534414

Message started by Go,TB on Aug 21^st, 2012, 12:33am

Title: instantiation inside analog block?
Post by Go,TB on Aug 21^st, 2012, 12:33am

I'm new to Verilog-AMS modeling and need helps to check my code as below.

What the main module means to do is just to delay the clock signal to a D-flip-flop, and then the output of the D-flip-flop is delayed as output of the main module.

//define D flip-flop
module adffp (d, clk, q)
......
......
endmodule

//main ckt module
module testx (inx, clk, outx);
input inx; voltage inx;
input clk; voltage clk;
output outx; voltage outx;
parameter real vh=1;
parameter real vl=0;
parameter real td=20n;

electrical clkdd; //internal net
electrical outdd; //internal net

analog begin
V(clkdd) <+ absdelay(V(clk), 2*td); //delay clk signal by "2*td"
adffp dffpx (inx, clkdd, outdd); //instantiation of adffp module with clkdd and inx
V(outx) <+ absdelay(V(outdd), 5*td); //delay outdd by "5*td" and then port it out
end
endmodule[/color]

The simulation is done by HSPICE and it complains that
"Syntax error, unsupported syntax or illegal keyword at/before 'dffpx', ..."

I wonder if it's legal to instantiate the module "adffp" inside analog behavior block. Is there better way to implement the function?

Thanks!

Title: Re: instantiation inside analog block?
Post by boe on Aug 21^st, 2012, 2:19am

Go,TB,
The module instantiation in your code does not comply with the LRM v2.3.1 (http://www.designers-guide.org/VerilogAMS/vams231.pdf), sec. 5.2 (syntax 5-1): Instantiation is not analog.

- B O E

Title: Re: instantiation inside analog block?
Post by Go,TB on Aug 21^st, 2012, 11:20am

Thanks for reply.

I checked the document you referred. It is like that I can't instantiate the module inside an analog block since the instantiation itself is not analog behavior.

I take the instantiation out of analog block and the code is like:

//define D flip-flop
module adffp (d, clk, q)
......
......
endmodule

//main ckt module
module testx (inx, clk, outx);
input inx; voltage inx;
input clk; voltage clk;
output outx; voltage outx;
parameter real vh=1;
parameter real vl=0;
parameter real td=20n;

electrical clkdd; //internal net
electrical outdd; //internal net

analog begin
V(clkdd) <+ absdelay(V(clk), 2*td); //delay clk signal by "2*td"
end

adffp dffpx (inx, clkdd, outdd); //instantiation of adffp module with clkdd and inx

analog begin
V(outx) <+ absdelay(V(outdd), 5*td); //delay outdd by "5*td" and then port it out
end
endmodule

This work-around can get the job done somehow. But I noticed a warning like:
port 'inx' declared, but not used

I can't figure out what's going on over there. Just guess that probably this is not best practice to implement the function.

Thanks!

Title: Re: instantiation inside analog block?
Post by boe on Aug 22^nd, 2012, 7:13am

Go,TB wrote on Aug 21^st, 2012, 11:20am:

This work-around can get the job done somehow.

Work around? It is specified behavior.

Quote:

But I noticed a warning like:
port 'inx' declared, but not used

I can't figure out what's going on over there.

I don't see any reason for this message in the code fragment you provided. It compiles nicely with my tools.
- B O E