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Design >> RF Design >> full rate or half rate for 65nm 5GBPS CDR
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Message started by elektra on Aug 22^nd, 2012, 10:33pm

Title: full rate or half rate for 65nm 5GBPS CDR
Post by elektra on Aug 22^nd, 2012, 10:33pm

which type of PD is good when compared to fullrate or halfrate PD? and similarly which one is good linear or bang bang(Digital) PD in 65 nm?

Title: Re: full rate or half rate for 65nm 5GBPS CDR
Post by BackerShu on Aug 23^rd, 2012, 10:00am

It's very hard to compare PD w.r.t to half rate or full rate, since both of them can implement these functions.

In terms of speed, Bang-bang PD has clear advantage since it's only limited by how fast a flip-flop can be built, whereas in linear PD, processing the very narrow pulse will limit the speed in the end, which can be very aggressive.

Of course, linear PD and Bang-bang PD have their own other problems also. Further, this paper may have some thing you want:

[1] R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” pp. 1–12.

Title: Re: full rate or half rate for 65nm 5GBPS CDR
Post by nrk1 on Sep 1^st, 2012, 9:58am

At 5Gbps, it should not be difficult to make a full rate CDR in 65nm. Full rate has simpler architecture and can be used unless limited by speed of the process. Bang-bang is probably easier-but fine details of the comparison can be got only by designing both in the same process.