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Design Languages >> Verilog-AMS >> Non-uniform sampling in VCO model
https://designers-guide.org/forum/YaBB.pl?num=1346020618

Message started by Praveen Prabha on Aug 26^th, 2012, 3:36pm

Title: Non-uniform sampling in VCO model
Post by Praveen Prabha on Aug 26^th, 2012, 3:36pm

Hi ,

I am trying to model a VCO based ADC using verilogAMS . The speed improvement is quite impressive compared to verilogA. However the VCO model that I tried from verilogAMS library from Designer's Guide seems to have an issue .

// Relevant section of the code

initial out = 0;

always begin
vin = V(ps, ns);
#(0.5e9 / (f0 + kvco * vin))
out = ~out;
end
endmodule
// End of code

When I try this model for the ADC , the spectrum has harmonics of the input which is affecting the SNDR performance especially at 12 bit levels . I believe this is due to the non-uniform sampling of the input waveform . The input variation within a VCO period is never taken into account in the model and the value of input is probed at different time instants.

Later I wrote a phase domain model of the VCO with the input sampled at regular intervals and with phase accumulation performed at every sampling instant. The phase also gets wrapped around at every PI and the sampling error is passed into the next cycle which helps in first order noise shaping of the sampling error. Relevant section of the code is attached.

//

initial

begin
phase_int=0;
tsample=5e-9; // Sampling time << Tvco/2
VOUT=0;
end

always #(1e9*tsample)

begin
phase_int=phase_int+2*`M_PI*tsample*(fc+Kvco*V(VCTRL));
if ( phase_int >`M_PI )
begin
VOUT=~VOUT;
phase_int=phase_int-`M_PI;
end
end
endmodule

//

The speed penalty is not much . I have attached the spectrum of output for a fair comparison.

Please comment on this issue.

Thanks,
Praveen

Title: Re: Non-uniform sampling in VCO model
Post by Ken Kundert on Aug 27^th, 2012, 10:24pm

Another approach it to simply tighten the time resolution using the `timescale command.

-Ken

Title: Re: Non-uniform sampling in VCO model
Post by Praveen Prabha on Aug 29^th, 2012, 7:19pm

Ken ,

Thank you.

I have used "`timescale 1ns/1fs " for both VCO models . In fact both of the models were simulated on the same test bench keeping all the parameters and tolerances same.

Do you expect the former model to give better accuracy than what I have got ?

Regards,
Praveen

Title: Re: Non-uniform sampling in VCO model
Post by Ken Kundert on Aug 29^th, 2012, 7:56pm

Yeah, I do. But you were getting better than 100dB of resolution even before you started making changes. At this level there are subtle low-level effects that make it hard to know what exactly is happening or how to get the best result.

In the future, you should really include your whole model. Leaving things out generally leads to uncertainty that make your question harder to answer and risk wasting peoples time. In this case, the `timescale is critical to the performance of the module, but you neglected to give it. Including the whole model would only have required a few more lines, but it would have removed considerable uncertainty. If you gave enough to duplicate your simulation (a short netlist), then you open up the possibility of getting really high quality feedback.

-Ken

Title: Re: Non-uniform sampling in VCO model
Post by Praveen Prabha on Aug 30^th, 2012, 9:11am

Ken,

Thank you.

I agree with you that I should have put the whole model to keep the question unambiguous. Will do in future.

Appreciate you help,
Praveen