The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> how to handle higher bias current??
https://designers-guide.org/forum/YaBB.pl?num=1346525480

Message started by raja.cedt on Sep 1^st, 2012, 11:51am

Title: how to handle higher bias current??
Post by raja.cedt on Sep 1^st, 2012, 11:51am

hello all,
due to some reason i have to use a NMOS with more than the current what it designed for (max contacts ratings), now i would like to ask if i flatten the PCELL and add some contacts will i get any problem?
I hope i can extract all the added contact resistance....

Thanks,
Raj.

Title: Re: how to handle higher bias current??
Post by fredd on Sep 3^rd, 2012, 2:43am

May I know what process you are using?

Title: Re: how to handle higher bias current??
Post by raja.cedt on Sep 3^rd, 2012, 4:49am

45nm...

Title: Re: how to handle higher bias current??
Post by Lex on Sep 3^rd, 2012, 7:00am

Except for model validity, I don't see really any reason why not. Of course as long as you obey to the DRC/DFM.

Could you give some extra details, e.g. how many extra contacts would you need, how many do you have, what is the current (density), etc..