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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> verilog ams ADC model with PSS https://designers-guide.org/forum/YaBB.pl?num=1348646176 Message started by conr on Sep 26th, 2012, 12:56am |
Title: verilog ams ADC model with PSS Post by conr on Sep 26th, 2012, 12:56am I have designed a very simple ADC model in verilog AMS. it works with dc and tran analysis but not with PSS. Anyone know why it happens and how to fix it? It is a problem of PSS analysis or something related to verilog AMS events? analog begin @(initial_step("dc")) begin if (dc_value==`LIMIT) begin dc_calc=V(vin)/vref*`LIMIT; end else begin dc_calc=dc_value; end mod[0]=dc_calc%2; div[0] = dc_calc /2; for (i = 1; i <= (`NUM_ADC_BITS-1) ; i = i + 1) begin mod[i] = div[i-1]%2; div[i] = div[i-1]/ 2; end V(vd7) <+ mod[7]*vlogic_high; V(vd6) <+ mod[6]*vlogic_high; V(vd5) <+ mod[5]*vlogic_high; V(vd4) <+ mod[4]*vlogic_high; V(vd3) <+ mod[3]*vlogic_high; V(vd2) <+ mod[2]*vlogic_high; V(vd1) <+ mod[1]*vlogic_high; V(vd0) <+ mod[0]*vlogic_high; end |
Title: Re: verilog ams ADC model with PSS Post by Geoffrey_Coram on Sep 27th, 2012, 12:24pm When I read this model, it looks like all the contributions (V(vd7) <+) are done inside the @initial_step block. I can't imagine how this model works at all, because these contributions do not persist after the first step. If you sweep (dc) or ramp (tran) the input, I don't see the module doing anything after the first point. |
Title: Re: verilog ams ADC model with PSS Post by conr on Sep 28th, 2012, 12:44am Hi Geoffrey, many thanks for your reply. I did a mistake coping the verilog model inside the topic. the real model had also a second section for transitorial analysis: @ ( initial_step("tran") ) begin halfref = vref / 2; end @ (cross(V(vclk) - vtrans_clk, 1)) begin unconverted = V(vin); for (i = (`NUM_ADC_BITS-1); i >= 0 ; i = i - 1) begin vd[i] = 0; if (unconverted > halfref) begin vd[i] = vlogic_high; unconverted = unconverted - halfref; end else begin vd[i] = vlogic_low; end unconverted = unconverted * 2; end end // // assign the outputs // V(vd7) <+ transition( vd[7], tdel, trise, tfall ); V(vd6) <+ transition( vd[6], tdel, trise, tfall ); V(vd5) <+ transition( vd[5], tdel, trise, tfall ); V(vd4) <+ transition( vd[4], tdel, trise, tfall ); V(vd3) <+ transition( vd[3], tdel, trise, tfall ); V(vd2) <+ transition( vd[2], tdel, trise, tfall ); V(vd1) <+ transition( vd[1], tdel, trise, tfall ); V(vd0) <+ transition( vd[0], tdel, trise, tfall ); The problem was the initialization of the variable halfref done just for "tran" simulation. I added "pss" in the initial_step function and now it works also for pss analysis. |
Title: Re: verilog ams ADC model with PSS Post by Geoffrey_Coram on Oct 1st, 2012, 6:30am I try to avoid initial_step for reasons such as this: you don't want to have to specify every possible analysis. A simple division is not much work, even if the simulator does it every iteration. Many compilers will optimize this away so that it only gets executed once. Alternately, you could use localparam halfref = vref / 2; |
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