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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> MOS capacitor for low voltage https://designers-guide.org/forum/YaBB.pl?num=1348748149 Message started by lhlbluesky_lhl on Sep 27th, 2012, 5:15am |
Title: MOS capacitor for low voltage Post by lhlbluesky_lhl on Sep 27th, 2012, 5:15am for nmos cap, when the voltage applied to its gate is very low, for example, the gate voltage is 0.4V for Vthn=0.65v, what is the problem? as i know, the capacitance may be smaller than high gate voltage case. any other influence? such as leakage, parasitic resistor, etc. besides, for very large resistor(larger than 1M ohm), it can have a large parasitic cap(1pF maybe). in my opinion, the parasitic cap comes from coupling between resistor and substrate, am i right? and how to calculate the parasitic cap for a given large resistor? and any difference for different type resistor? thanks. |
Title: Re: MOS capacitor for low voltage Post by boe on Oct 1st, 2012, 11:54pm Hi lhlbluesky_lhl, See e.g. Razavi. All the usual effects apply. Usually, yes. RTFM. Yes. - B O E |
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