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Modeling >> Behavioral Models >> Parametrized busses in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1349372461

Message started by radius2 on Oct 4^th, 2012, 10:41am

Title: Parametrized busses in Verilog-A
Post by radius2 on Oct 4^th, 2012, 10:41am

Hi

I'm trying to create an instance with a parametrized bus
in Verilog-A i. e. when I instantiate it in a schematic in cadence,
then there should be a parameter to determine the size of
the bus by clicking on the instance and pressing Q. The idea is to avoid creating several instances with the same functionality but with different
bus sizes. However, I'm wondering if this is possible. What would
happend with the bus pin when the symbol is created?

I've come across a few ways that give some clues for example:

module adc(out, in, clk);
.
.
parameter integer bits = 8; // resolution (bits)
.
.
output [0:bits-1] out;
electrical [0:bits-1] out;

This however generated the following error:
"Encountered missmatch in size of formal and actual for out,
make sure the size of formal and actual match"

Another example I found, used the line `define bits 8
before the line module adc(out, in, clk);, instead of defining
bits as a parameter. However this doesn't
include the possibility to change the bus size when putting the instance
in the schematic.

So before I discard the idea completely I wanted to ask here if
this is possible to do.

Title: Re: Parametrized busses in Verilog-A
Post by boe on Oct 5^th, 2012, 5:44am

radius2,

Verilog-A should allow parameterized bus widths for ports and signals.

However, the Cadence Verilog-A implementation does not seem to support this: According to Cadence Verilog-A reference v11.1 (Sept 2011), "parameter-sized ports" are not supported by their implementation.

- B O E

Title: Re: Parametrized busses in Verilog-A
Post by radius2 on Oct 5^th, 2012, 7:49am

Ok good to know. Thanks for your reply.
I'll go on creating instances with different number
of bits instead.

Title: Re: Parametrized busses in Verilog-A
Post by Frank Wiedmann on Oct 8^th, 2012, 1:15am

You might want to check if you can adapt the approach using symbol and schematic pcells which was used for the bussetp component for your purposes (see http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11696480).