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Design >> Analog Design >> BGR comparison
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Message started by yvkrishna on Oct 9^th, 2012, 2:44am

Title: BGR comparison
Post by yvkrishna on Oct 9^th, 2012, 2:44am

hi,
The two figures shown in the pic here can be used for BG voltageReference design.
what is the purpose of having that additional resistor in series with pmos curr source?

Thanks,
yvkrishna

Title: Re: BGR comparison
Post by Dan Clement on Oct 9^th, 2012, 3:56am

To consume area, lower headroom, and generate noise.

Title: Re: BGR comparison
Post by yvkrishna on Oct 9^th, 2012, 4:04am

sorry, I meant to say that I have noticed designers using both of these for designing BGR and was trying to understand if there is any special advantage of having that additional resistor.

Title: Re: BGR comparison
Post by amarnathdinamani on Nov 13^th, 2012, 4:41am

The resistor sitting below the current source will boost the output impedence seen at the output of the BGR (I mean at the point BG=IPTAT*R2+VBE). Just run psrr sims ,you will notice the difference. Your dc psrr should get boosted because of this resistor, ac though will get determined by capacitor at the output.

Thanks...

Title: Re: BGR comparison
Post by yvkrishna on Nov 29^th, 2012, 8:19am

@analog_wiz,

could you elaborate your explanation about psrr, i dont understand the psrr improvement with hi o/p impedance?

Also the o/p impedance should have to be same (assume both cases are designed for same o/p voltage , so the total resistor whether split/not has to be same.)

I feel that its just for the convenience of trimming one single resistor instead of two.

Thanks,
yvkrishna

Title: Re: BGR comparison
Post by analog_wiz on Nov 29^th, 2012, 11:41pm

By output impedance i meant the impedance seen from ac power supply to your output node(this is boosted by the resistor R which is not present in the second topology)

Always look at psrr simplifiedly (although as such not so simple) in terms of voltage division: you can look it as power supply noise getting voltage divided between two impedances(one from supply to output node and another from output node to the ground). PSRR(DC) will depend on the impedance from supply to the output node (if you have source degeneration then its as good as improving the psrr Ro=r0+Rs+gm*r0*RS. Hence dc psrr improves. AC PSRR(At 1MHz) at frequencies before UGB of the opamp is dependent on the opamp first pole. So try moving the dominant pole without compromising stability (lower current mean very less BW hence poor ac psrr ,which is not uncommon for bandgaps). To cater to higher frequencies size a capacitor and place it at the output so that it can shunt out noise a higher frequencies to the ground.How big a cap(huge area) determines how good a psrr you can achieve at higher frequencies beyond the UGB of the opamp.Other than this there are many other techniques such pre-regulating supply,etc which can give still higher psrr at dc and 10k.

Title: Re: BGR comparison
Post by RobG on Nov 30^th, 2012, 9:16pm

I think the output is supposed to be taken at the MOS drain. In that case the resistors can be sized so that they two circuits are nominally identical at DC, but the circuit on the left uses less resistor area.

Here is an example. Say the current splitting resistors on the right circuit are each "R". The circuit on the left would be equivalent if the red resistor was R/4 and the splitting resistors were each R/2. In that case the total resistance for the left circuit would be 1.25*R compared to 2*R for the right circuit, so nearly a 2x savings.

The downside of doing this is that as the current splitting resistors become smaller the circuit becomes more sensitive to the opamp input noise and offset. To see this consider how the performance would change if you had 1 mV offset on the opamp. If the nominal drop across the splitting resistances was 500mV the current in each leg would mismatch about 1/500. However if you cut the splitting resistors in half the drop will be 250mV, and your current mismatch will be ~1/250.

The R/4 and R/2 circuit example I gave is a reasonable trick to cut resistor area, but you have to check the noise and Monte Carlo performance to make sure the benefits aren't outweighed by the noise and offset.

rg

Title: Re: BGR comparison
Post by analog_wiz on Dec 1^st, 2012, 8:49pm

krishna, are u trying to depict the original topology in the figure or an equivalent circuit. I have not seen this topology in any paper. Will be useful if you could provide a link for the same, if available.

Title: Re: BGR comparison
Post by mists on Dec 7^th, 2012, 9:04pm

Then for the right one, how about use two PMOS transistor for the two path instead of only one PMOS transistor. Regards the opamp offset, is the one PMOS output better than two PMOS transitor? thanks!

Title: Re: BGR comparison
Post by mists on Dec 16^th, 2012, 5:40am

mists wrote on Dec 7^th, 2012, 9:04pm:

who can give me some clue, thanks!

Title: Re: BGR comparison
Post by RobG on Dec 16^th, 2012, 12:33pm

mists wrote on Dec 7^th, 2012, 9:04pm:

Opamp offset affects accuracy in two ways: 1) changing the ratio of the right/left legs; and 2) adding directly to the delta-Vbe (PTAT) voltage generated across the resistor that sets the current.

Using two PMOS devices to split the current would essentially eliminate the opamp's contribution to (1), but (2) is a bigger contributor to the overall error. In addition, now you can't draw any current from the output or you will change the ratio of currents.

Title: Re: BGR comparison
Post by mists on Dec 17^th, 2012, 4:56am

RobG wrote on Dec 16^th, 2012, 12:33pm:

then you mean that use one PMOS output better than two PMOS transistors?thanks!

Title: Re: BGR comparison
Post by yvkrishna on Jan 1^st, 2013, 1:45pm

Thanks everyone for the replies and suggestions.

@RobG,
Thanks, this is what I was looking for, yes mismatch/noise is better for case with larger current split resistor.
as the addnl contributor from amp offset is prop. to voff/r_split .

@analog_wiz,
I dont have any paper, saw it in some old design.

@mists
May be its fair to compare these 2circuits in the fig here
a) 2 pmos current sources for current split.
b) 1 pmos current source(2x sized) and resistors for current split.

Assuming both are designed for same nominal DC conditions, and major mismatch sources are current mirror, opamp offset.
(a) is better if pmos current mirrors mismatch is small and opamp offset dominates.
(b) is better if mirrors dominate the total o/p referred offset.

because in case (b) thers an additional source of mismatch due to improper current split (with a difference of voff/r_split) even though the pmos mir mismatch is minimised by the loop.

regards,
yvkrishna