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Simulators >> Circuit Simulators >> Modeling a non-ideal power supply in LTSpice
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Message started by akylik on Oct 10^th, 2012, 5:15am

Title: Modeling a non-ideal power supply in LTSpice
Post by akylik on Oct 10^th, 2012, 5:15am

When simulating a circuit in LTSpice, I would like to see the noise generated on my power bus by fast changes in current draw and then see the noise filtered when I add bypass capacitors. I thought I could do this by adding the ESR, ESL and parasitic capacitance to my ideal voltage source. Once I add ESR for example I do see "noise" on the power bus but adding a bypass capacitor of any value doesn't seem to affect anything. I've attached an image of the circuit that I'm working with. V+ is the power bus. C1 is the bypass capacitor. V2 is the ideal voltage source that I'm trying to make non-ideal, currently ESR=3ohms and I've added L1 to model the supply inductance. The value of C1 is being stepped over in repeated simulations to see its affect on the transient of V+ but there is no appreciable change.

Title: Re: Modeling a non-ideal power supply in LTSpice
Post by Geoffrey_Coram on Oct 12^th, 2012, 5:56am

Have you tried larger values of C? It looks like you're stepping it from 0.01u to 0.1u, but the Cpar value you've assigned to the V2 source is 1u, that is, 10x the size of your bypass cap. Try something like 100u just to see what happens.