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Design >> Analog Design >> properties of stacked mos device
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Message started by yvkrishna on Oct 13^th, 2012, 2:24pm

Title: properties of stacked mos device
Post by yvkrishna on Oct 13^th, 2012, 2:24pm

Hi everyone,

In shorter geometries as the max lengths get limited people started using stacked mos devices to increase effective length(mosfets in series to increase the length analogous to mos in parallel for increasing total width)

Is there any basic reference document for understanding the properties of this composite device (series stack) like effective vth,vdsat, parasitics, mismatch,noise etc.

Ex: W/L in series with W/L is equivalent to device of W/2L dimensions.

--To a first order we expect this composite device behaves like a single device with effective length of 2X, is it true for all properties of device?

-- can we really use devices of different lengths ?
is W/L1 stacked with W/L2 equivalent to W/(L1+L2)??

Thanks,
yvkrishna

Title: Re: properties of stacked mos device
Post by raja.cedt on Oct 15^th, 2012, 7:45am

hello,
1. yes, when you have W1/L1 and W2/L2 size transistors the resulting
transistor size from DC characteristics point of view L/W=L1/W1+L2/W2.

2. Effective Vt will be same as top transistor.
3. Coming to device intrinsic mismatch up to it is not effective, the normal saying of larger effective length will not work here. Look reduction of mismatch with bigger size comes from the random averaging theory, instead here effectively you are increasing the size.
Let us model bottom triode transistor as a resister (for now assume there is no modulation of resistance due to drain voltage variation). In the contest of degeneration mismatch of the top transistor will be reduced but resister mismatch will introduced, however resister matches better but here this resister emulated by again Mosfet.

4. Noise is worse, because same reason mos noise worse than degeneration.

So bottom line is this combination will be good from low voltage operation point of view and may be worse from other aspects.

Thanks,
raj.

Title: Re: properties of stacked mos device
Post by yvkrishna on Nov 27^th, 2012, 8:02am

Thanks raja for your inputs.

1.Yes L/W =L1/W1 +L2/W2

3. But for mismatch I could very well correlate my monte simulation results with a device of effective length and wdith (sim matches well for nmos/pmos across various sizes, bias , number of stacks etc)

Thanks,
yvkrishna

Title: Re: properties of stacked mos device
Post by rfidea on Nov 27^th, 2012, 11:26am

I agree with raja that in principle you can add the two lengths. But I wonder why you would like to stack two devices. I would have increased the length and only use one transistor. Usually there is some limitation in the design kit, but that is the length need to be shorter than some 25 um or so.

Title: Re: properties of stacked mos device
Post by yvkrishna on Nov 27^th, 2012, 11:35am

@rfidea,

Here I am talking about advanced process nodes with max length not even 5um.

Title: Re: properties of stacked mos device
Post by rfidea on Nov 27^th, 2012, 1:19pm

Aha, I did not know that Lmax was that low for those processes. I do not understand why, though. Is there any technical reason other than logistical such as testing and modeling efficency.

Title: Re: properties of stacked mos device
Post by raja.cedt on Nov 27^th, 2012, 2:54pm

hello vamsi,
I didn't have ans for mismatch reduction. Whats your simulation setup, have you observed noise reduction simply by replacing mosfet by stacked mosfet? or any modification. If this is the case then realizing good cascoding with lesser voltage head room could be posb, try to use this.

Thnaks,
Raj.

Title: Re: properties of stacked mos device
Post by analog_wiz on Nov 27^th, 2012, 7:19pm

I dont think there is any limit on the length say 5u in smaller gomentries. The only time i use devices in series is to get some very small current mirrored eg:1/2:1/8 (1/8=four 1/2 devices in series).

Title: Re: properties of stacked mos device
Post by Lex on Nov 28^th, 2012, 12:59am

Max 5um length is surely a modelling 'thing'.
However for some other layout topologies (such as ELT), there is no other choice than stacking since naturally you have a large effective W/L.

Title: Re: properties of stacked mos device
Post by raja.cedt on Nov 28^th, 2012, 6:44am

@ analog_wiz,
Can you please explain clear why did you use stacked devices?,i were you i would have done 2:1 mirroring directly rather than using stacked devices, up to me stacked device is equivalent to larger length device, but up to me mismatch will be bad for this combination.

Did you find any reduction in the noise or mismatch, because yvkrishna noticed reduction in mismatch i just want to check is it consistent with every one.

@Lex : i heard mainly fabrication limitation due to introduction of Double-pattern lithography metal gate technologies in lower technologies and orientation limitation due to modeling(i am not sure) . What is ELT?

Thanks,
Raj.

Title: Re: properties of stacked mos device
Post by Lex on Nov 28^th, 2012, 8:13am

@raja.
An ELT MOSFET is where you have the gate completely surrounding the drain. Here is a simple diagram:

Title: Re: properties of stacked mos device
Post by raja.cedt on Nov 28^th, 2012, 8:42am

hello Lex,
interesting, this i knew this with name donnet transistor, but haven't seen in any technology.Which foundry is providing this?

Thanks,
Raj.

Title: Re: properties of stacked mos device
Post by carlgrace on Nov 28^th, 2012, 9:06am

raja.cedt wrote on Nov 28^th, 2012, 8:42am:

hello Lex,
interesting, this i knew this with name donnet transistor, but haven't seen in any technology.Which foundry is providing this?

Thanks,
Raj.

You can make an ELT in any process you just have to lay it out by hand (it won't be included as a pcell in the pdk). You probably have to do a test chip to characterize their performance if you have critical requirements in your application.

They are primarily used for radiation hardness as they are more tolerant of total dose radiation than standard layouts.

Title: Re: properties of stacked mos device
Post by yvkrishna on Nov 28^th, 2012, 9:38am

pls see this in fig5 and the text above it.

http://www.design-reuse.com/articles/28591/mixed-signal-ip-design-challenges-in-28-nm-and-beyond.html

Title: Re: properties of stacked mos device
Post by analog_wiz on Nov 28^th, 2012, 10:15am

i used devices in series to generate very less current: say i have 1u through (1u/2u)transistor and i need to generate 1/4 the current, then i would use (1u/2u) four of them connected in series. Would be interested in hearing if there were any other better methods of generating very low current from a given current.

Title: Re: properties of stacked mos device
Post by rfidea on Nov 29^th, 2012, 12:35pm

One solution is to use four transistors in parallel of W/L=1u/8u as reference transistor with 1uA and then one 1u/8u transistor for the 1/4 uA transistor. Larger layout but probably better matching.

Title: Re: properties of stacked mos device
Post by analog_wiz on Nov 29^th, 2012, 11:35pm

But will it not be bad in the sense that the vth of a 1u/8u and 1u/2u device will not be the same and will lead to a systematic current mismatch error?

Title: Re: properties of stacked mos device
Post by rfidea on Nov 30^th, 2012, 1:38pm

Not if you implement the 4x 1u/8u transistor as four unique transistors. Then the current density of each of them will be the same as the single 1u/8u, which give the same vth and good matching.

Title: Re: properties of stacked mos device
Post by raja.cedt on Dec 2^nd, 2012, 5:14pm

hello rfidea,
i guess Vth mismatch will be serious problem in this case. How current density related to Vth (from your previous post).

Thanks,
Raj.

Title: Re: properties of stacked mos device
Post by rfidea on Dec 3^rd, 2012, 11:29am

Of course, for the specific current the W/L ratio needs to be chosen so the Vgs-Vth voltage is high enough to get the wanted Vth mismatch.

Title: Re: properties of stacked mos device
Post by threepwood on Mar 23^rd, 2013, 6:39am

Interresting topic
Can someone provide mathematical calculation to prove it?

I would extend the question for robust cascode polarization technique below:

I know it works fine, but I've never managed to calculate why. I also think that the 2 (or 3, or 4,...) devices at the bottom (that are in triode region) must match the NMOS bias device...

Can someone try to do the calculations? :)

Title: Re: properties of stacked mos device
Post by tzg6sa on Mar 23^rd, 2013, 12:51pm

I doubt whether any calculations should give you a good enough precision. Nowadays the square law MOS characterisitc is far from precise and also you will have one transistor in saturation and all the other in triode region not far from the saturation region.

Title: Re: properties of stacked mos device
Post by tzg6sa on Mar 23^rd, 2013, 12:52pm

Here is an older topic:
http://www.designers-guide.org/Forum/YaBB.pl?num=1162979112

Title: Re: properties of stacked mos device
Post by threepwood on Mar 23^rd, 2013, 1:08pm

Horror Vacui wrote on Mar 23^rd, 2013, 12:51pm:

They are all deeply linear (with VDS=5,10,15mV,..) and the device at the top, even if the square law is not accurate, I just would like to get a trend