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Design >> Analog Design >> Idea of using current mode BGR to avoid v2i design
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Message started by yvkrishna on Oct 13^th, 2012, 3:21pm

Title: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 13^th, 2012, 3:21pm

Hi everyone,

Usually voltage mode bandgap is designed which is followed by a V2I block to generate currents for providing to all parts of the chip.

Instead if we use a current mode BGR we could get directly generate zero TC current, isn't this beneficial in-terms of area,power,errors of this additional V2I block?

Are there any preliminary considerations for budgeting this?

Thanks,
yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by ywguo on Oct 15^th, 2012, 6:24am

Hi yvkrishna,

What is the schematic or structure for your current mode BGR? I have no idea that generate a zero TC current with a current mode BGR.

Best Regards,
Yawei

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 15^th, 2012, 8:23am

Hi Yawei,

please look into this paper
http://www.ing.unibs.it/~richelli/matpdsia/bg1.pdf

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by rfidea on Oct 15^th, 2012, 1:31pm

It looks like the BGR circuit you refer to generates a voltage and then a current proportional to that voltage. No true current BGR. There is no such thing, not yet discovered anyway.

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 15^th, 2012, 1:57pm

@rfidea,

There is no voltage generated here in the BG loop.(infact zero TC current is used to generate voltage here)
If you are referring to current leg with M2+R20 in the figure it also mirrors current from the BGcore and then creates a voltage.
So this generated voltage has nothing to do with the current generation.

Please let me know if I understood your comment correctly.

--yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by ywguo on Oct 15^th, 2012, 7:43pm

As what rfidea said, that is not true current BGR. I mean that there is not any zero TC current in that BGR.

Yawei

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 15^th, 2012, 9:31pm

@rfidea,

could you please elaborate your comment.

I dont find any reason for not having zero TC current in the BG core shown (pls see the currents marked in the fig).

If we work it out completely there is a dependency of resistor TC on the current which we generate, other than that its very much same as conventional voltage Bandgap.

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by boe on Oct 16^th, 2012, 2:14am

yvkrishna wrote on Oct 15^th, 2012, 9:31pm:

...
If we work it out completely there is a dependency of resistor TC on the current ...

That is the point!
- B O E

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 16^th, 2012, 2:55am

Hi BOE,
We can always calculate the modified condition for achieving zero temp coeff in the presence of finite TC for resistors.

my observation so far is that the impact of resistor TC is not so much(ofcourse it depends on process one uses) for achieving ZTC current.

What else is the limitation?

Thanks,
yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by boe on Oct 16^th, 2012, 6:34am

yvkrishna,

your circuit creates a weighted sum of VBE and VT across R20. So it is a bandgap (if properly scaled). Iout is generated by converting the bandgap voltage converted to a current through R20.

So it is a V2I design, too

- B O E

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 16^th, 2012, 8:49am

I agree with BOE, so its inherently present in the same circuit.

And so my query comes- why cant we just design this to avoid additional v2i block design altogether.

-yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by boe on Oct 16^th, 2012, 10:20am

Because (as rfidea already pointed out) "[t]here is no such thing, not yet discovered anyway."
- B O E

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by rfidea on Oct 16^th, 2012, 1:13pm

It looks like everything is said in this matter. What I mean is that there is a principal difference if your circuit first generates a voltage and then a current proportional to that voltage, compared to a circuit that directly generates the current. The first exist, it is a BGR, the second does not, not yet anyway.

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Oct 18^th, 2012, 2:24pm

sorry guys may I should not have called it as currentmode BGR, rather its just a current summing BGR.

let me re-frame the question which I am actually looking to get inputs for :
A current reference can be generated in 2ways
(1). use conventional voltage BGR (which gives ~1.2V output)and follow it with an explicit v2i block which typically has an opamp with current source+resistor)
(2). use the BGR shown in the fig above.

In case (2) we can altogether avoid designing this additional errorAmplifier in v2i stage which looks easier and better in terms of area,power and all errors(noise,offsets) introduced by this block.

Is this idea correct?

-yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by boe on Oct 19^th, 2012, 12:00pm

yvkrishna,

what about PSRR and matching of M0/M1?

- B O E

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Nov 1^st, 2012, 12:25pm

BOE,

PSRR and matching of M0/M1 is present in both the cases 1,2.

what is your intention?

thanks,
yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by boe on Nov 3^rd, 2012, 2:17pm

yvkrishna,

Sorry, I was in a hurry when I wrote that.

I was trying to make the points that
1) you should look at the PSRR of that circuit (might be worse than conventional BGR [depending on opamp]),
2) the current matching in M0/M1 is critical to the performance of the BGR, and
3) at the same current, current noise of M0/M1 is larger than current noise in resistors of conventional BGR.

- B O E

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by RobG on Nov 5^th, 2012, 10:26am

yvkrishna wrote on Oct 16^th, 2012, 2:55am:

yvkrishna,
I've done this many time and it works fine. Like you figured out, you have to account for the TC of the resistor, but this is true even if you use a voltage to generate the current (your voltage TC has to be the same as the resistor TC.

The first consideration is that it is difficult to trim the TC with a single measurement. If you were doing a voltage-mode reference you can room temperature trim to a "magic" voltage that will give you zero TC for all errors except opamp offset. After that you would trim out the error due to the sheet resistance in your V to I circuit.

The second consideration is that with a current reference you would be trimming the magnitude and TC of the current simultaneously. While you can measure the current directly and trim it to spec, the resulting temp co will depend on how much of the error is due to sheet resistance variation or opamp offset, mismatch and bipolar IS variation. One way to get around this problem with the circuit you showed is first trimming the voltage across R20 (e.g. by varying the ratio of M1 and M0) to the "magic" voltage, and then trimming the output current by sizing M22.

Hint - when trimming don't actually change M0/M1/M22 sizes, but instead put a current dac in parallel with them that is biased with a smaller current scaled from the main current.

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Nov 21^st, 2012, 10:02pm

RobG,
Thanks for sharing your experience with this kind of circuit.
Is there any other design challenge with this architecture while trying to generate both voltage an current with decent accuracy.

thanks,
yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by analog_wiz on Nov 21^st, 2012, 11:03pm

Take care that you have adequate trim range both ways(ctat slope as well as ptat slope,both abs trim as well as tempco trim).Bandgaps look great in simulation,but model inaccuracies can make it tough.Also take care to have metal options in case you need to fib and do some testing before you decide to fix a problem.

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by yvkrishna on Mar 17^th, 2013, 10:34am

Hi RobG,

I am a bit confused with your suggestions about trims.

"First trim the voltage across R20 by varying ratio of M1&M0" how will this work ?

Also trimming the current using a small current dac in parallel has a limitation on how small the trim step is ?

ex: how can I get 0.5% trim in currents ? (which is a big ratio for current mirror). I have asked for 0.5% trim because I need the same step size in voltages which I generate.

Thanks,
yvkrishna

Title: Re: Idea of using current mode BGR to avoid v2i design
Post by Kevin Aylward on Jul 6^th, 2013, 6:53am

Yes, it is perfectly feasible to generate a temperature independent current without and bandgap voltage appearing anywhere in the circuit, despite some of the claims in this thread. But why would this need to be done? All real systems need a reference voltage, so might as well use it! On a technical side, there are techniques in BG design for getting very low noise, that would probable not be mimicable in current mode. Regarding TC, 1st order TC of the resister is not important as it can be taken up in the wash when setting the current cancelling TCs. There is actually a simulation example for the current summing bandgap technique in SuperSpice.