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Simulators >> RF Simulators >> PLL PSS/PNoise simulaton
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Message started by Lynn Lou on Oct 15^th, 2012, 7:16pm

Title: PLL PSS/PNoise simulaton
Post by Lynn Lou on Oct 15^th, 2012, 7:16pm

Hi,

Since PSS/PNoise simulaiton using SpectreRF for PLL(only the reference clock uses VerilogA block) consumes time while runs into convergence problems always, people simulate PSS/PN for separated modulus in PLL.

It's relatively easier to get VCO PSS/PN, but I can't simulate for the rest of the modulus, the divider/PFD/CP, etc., since convergence problems always there. Is there any specific setup for PSS/PN simulation? Take the divider for instance, I set the output freq as the beat freq, and what about other setup?

Thank you very much!

Lynn

Title: Re: PLL PSS/PNoise simulaton
Post by RFICDUDE on Oct 16^th, 2012, 4:37am

I don't have specific experience with simulating PLLs with PSS, but I do know that PSS convergence is sensitive to the value of "tstab" when simulating switched circuits such as dividers, PFD and inverters.

The PSS start and finish points for the fundamental need to be on the rising or falling edge of a signal that is periodic with fundamental. PSS iterates to make the start and finish point the same. If the beginning and endpoints are at the max or min value of a clock then PSS cannot determine a unique point where the signal is periodic (any change yields the same answer).

I generally try to pick a tstab that starts the period on a rising or falling edge of the highest frequency clocked/limited signal.

A completely different suggestion:
You could try using "transient noise" analysis with APS to simulate noise. The down side is that transient noise cannot tell you who the individual contributors to the noise total, but (on the positive side) you can probe noise anywhere in the circuit.

Good luck

Title: Re: PLL PSS/PNoise simulaton
Post by Ken Kundert on Oct 16^th, 2012, 11:21am

Does your PLL have periodic steady state behavior?

Title: Re: PLL PSS/PNoise simulaton
Post by Lynn Lou on Oct 16^th, 2012, 11:12pm

RFICDUDE wrote on Oct 16^th, 2012, 4:37am:

...but I do know that PSS convergence is sensitive to the value of "tstab" when simulating switched circuits such as dividers, PFD and inverters.

The PSS start and finish points for the fundamental need to be on the rising or falling edge of a signal that is periodic with fundamental.

Thanks RFICDUDE,

Does that means that if I want to simulate PSS for a PLL, I should set "tstab" much larger than the PLL lock time? It really costs lots of time.

The other question is, if I simulate PSS for a divider, which takes a VerilogA frequency source as its freq input, theorically, the output freq is stable, so can I set "tstab" to a small value or just leave it blank?

Yes, trans noise is convenient to get, but I think it has little relationship with Phase Noise, right?

Thank you~

Title: Re: PLL PSS/PNoise simulaton
Post by Lynn Lou on Oct 16^th, 2012, 11:15pm

Ken Kundert wrote on Oct 16^th, 2012, 11:21am:

Does your PLL have periodic steady state behavior?

Thanks kundert,
My PLL has PSS behavior. I think all PLLs have PSS behavior after it locks, right?

Thank you~

Title: Re: PLL PSS/PNoise simulaton
Post by Ken Kundert on Oct 17^th, 2012, 1:49am

No. If the phase detector has a dead zone it will not exhibit periodic behavior. If it is a fractional-N synthesizer it will not exhibit periodic behavior. If the PLL is unstable or is subject to a non-synchronous interferrer it will not exhibit periodic behavior.

The easiest way to test this is to run a long transient analysis with strobing turned on. The strobe period should be the expected PSS period. All signals when strobed at the fundamental frequency should eventually become constant valued. If any signal is not asymptotically approaching a constant value then the PSS analysis will not converge. At the minimum you should examine the VCO control signal, the VCO output frequency, and the supply currents.

-Ken

Title: Re: PLL PSS/PNoise simulaton
Post by Lynn Lou on Oct 17^th, 2012, 8:03pm

Thanks Ken,

Ken Kundert wrote on Oct 17^th, 2012, 1:49am:

I believe my PLL has PSS behavior, considering the conditions above.

And what is the "strobing" while transient analysis? How can I achieve it?

Thanks a lot.

Title: Re: PLL PSS/PNoise simulaton
Post by Ken Kundert on Oct 17^th, 2012, 11:28pm

Do you know what a strobe light is and what it is used for? Strobing is the Spectre equivalent. Just set strobeperiod=T. This will cause Spectre to only output time points that are at times that are exact multiples of T. In other words, the computed waveforms are sampled every T and the sampled waveform is output rather than the original waveform. If your signals are T-periodic, then they should appear constant valued when sampled every T seconds. If they are not asymptotically approaching constant valued then your PLL is not exhibiting a T solution.

-Ken

Title: Re: PLL PSS/PNoise simulaton
Post by Aman on Oct 18^th, 2012, 1:23pm

Hi Ken,

Can you elaborate more on this or perhaps suggest a read?
PSS convergence is a big problem, with bang-bang PD's in
general; are there any settings that will cause convergence
when we have a lot of limit-cycle behavior in the steady-state
for synthesizer circuits. Also with CP-PLL we can have lot of
spur content at fout/N*M, how will that work with PSS.

Thanks,
Aman

Title: Re: PLL PSS/PNoise simulaton
Post by Ken Kundert on Oct 18^th, 2012, 11:49pm

By their very nature bang-bang CDRs exhibit chaotic behavior and so will never converge in a PSS analysis. What I know about simulating bang-bang CDRs I have written up and published in http://designers-guide.org/Analysis/bang-bang.pdf. If you need anything more that that, you need to be more specific.

-Ken

Title: Re: PLL PSS/PNoise simulaton
Post by Lynn Lou on Oct 19^th, 2012, 8:15am

Ken Kundert wrote on Oct 17^th, 2012, 11:28pm:

...This will cause Spectre to only output time points that are at times that are exact multiples of T. In other words, the computed waveforms are sampled every T and the sampled waveform is output rather than the original waveform.
...

Thanks Ken,

Will this "strobeperiod" setting helps to improve the convergence in PLL PSS simulation? Or it is just a judgement for convengence?

Thanks a lot~