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Design Languages >> Verilog-AMS >> Clock generator with variable period in Verilog-A
https://designers-guide.org/forum/YaBB.pl?num=1350570381

Message started by gsensor on Oct 18^th, 2012, 7:26am

Title: Clock generator with variable period in Verilog-A
Post by gsensor on Oct 18^th, 2012, 7:26am

Hi everyone,

I don't use Verilog-A to often, and I'm simply trying to write a clock generator code in Verilog-A with a variable period that changes at fixed time (tend3 and tend 4). It is also activated by an input enable signal. When en input is higher than 1 V, the clock is generated in the output signal (out), else, the output signal (out) goes to 0V. The out signal (or CLK) has a maximum amplitude of 2V.

Here's my code

Code:

`include "constants.vams"
`include "disciplines.vams"

module clk_generator_va(en,clk);

parameter real tt = 0n; // output transition time (s)
parameter real t3 = 500n;
parameter real t4 = 1u;

output out;
input en;
voltage out,en;

real Vout,td,tend,tend2, tend3, tend4;

analog begin

@(initial_step) begin
Vout = 0;
td =2.5n; //time 0, clk_period = 5ns
tend = $abstime + td;//return simulation time + td
tend2 = $abstime + td +td;//return simulation time + 2td
tend3 = $abstime + t3;//return simulation time + t3
tend4 = $abstime + t4;//return simulation time + t4

end
@(timer(tend)) begin

if (V(en) < 1) //Check en condition, if en<1V, Vout = always 0V
Vout =0;
else //Else, Vout=2V and a clock is generated at out.
Vout = 2;
end

@(timer(tend2)) begin
tend = $abstime + td;//return simulation time + td
tend2 = $abstime + td +td;//return simulation time + td
Vout = 0;

end

@(timer(tend3)) begin

td = 5n;// clk_period change to 10ns.
end

@(timer(tend4)) begin
td = 10n;// clk_period change to 20ns.
end

V(out) <+ transition(Vout, td, tt);
end
endmodule

I get a response varying depending on the transient simulation time I set. When I simulate for 1.1 us it works fine, with a VDC source attached to en..(see picture 1). Although, if I simulate for 20 us, I get an output signal with a maximum amplitude of 1V (see picture 2).
When I vary en from 0 to 2.5V every 4 us using vpulse source attached to en, I get an output signal of 200 mV (see picture 3).
It must be a parameter to set for the simulator, but which one ?

I use Spectre simulator in Cadence version 5.1.4 -USR6

How do I fix this ?
Thanks,
gsensor.

Title: Re: Clock generator with variable period in Verilog-A
Post by gsensor on Oct 18^th, 2012, 7:26am

Picture 1:
With en = 2.5 V

Title: Re: Clock generator with variable period in Verilog-A
Post by gsensor on Oct 18^th, 2012, 7:40am

Picture 2:

With en = 2.5V and total simulation time is 20 us (althougth only the first 3 us is shown here to allow a better visualisation of the signal..)

Title: Re: Clock generator with variable period in Verilog-A
Post by gsensor on Oct 18^th, 2012, 7:41am

Picture 3:

With en varied every 4 us, using a vpulse source attached to input en.

Title: Re: Clock generator with variable period in Verilog-A
Post by Ken Kundert on Oct 18^th, 2012, 10:00am

Your asking for trouble by setting the transition time of the transition filter to 0. I recommend you start by giving it a reasonable value. I also think the logic behind your oscillator is not correct. I recommend that you start from a working oscillator and hack it up until you get what you want. Try looking at the Verilog-AMS page on this site. In particular, you can find fixed-frequency oscillators in http://www.designers-guide.org/VerilogAMS/functional-blocks/osc/osc.va.

-Ken

Title: Re: Clock generator with variable period in Verilog-A
Post by boe on Oct 19^th, 2012, 11:52am

Gsensor,

Two additional things: a) 5.1.41USR6 for the spectre is quite old.
b) the delay of the transition filter seems suspect to me.

- B O E