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Design >> Mixed-Signal Design >> Competitive Chip Design - A "must read" for all designers.
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Message started by loose-electron on Oct 20th, 2012, 8:10pm

Title: Competitive Chip Design - A "must read" for all designers.
Post by loose-electron on Oct 20th, 2012, 8:10pm

If you are an IC designer you really should read this:

http://electronicdesign.com/article/analog-and-mixed-signal/marketing-technology-collide-competitive-chip-design-74546

I wrote this particular article after many years of
seeing designers violate the rules I outline in the article.

You want to design chips that sell in the millions?
You need to read it.

Also, while you are there hit the "like" button, and
post any questions there and I will answer them.

Thanks,

Jerry

Title: Re: Competitive Chip Design - A "must read" for all designers.
Post by Lex on Oct 22nd, 2012, 4:02am

I appreciate the article, and has some parts that I recognize at the spot (e.g. the 'Not invented here syndrome'). However, I feel some things are left out in the article.

The most important thing I miss:

The trade off between verification time and time to market. Of course 'first time right' is everybody's goal, but for more and more complicated chips it is not that easy and well defined. In my experience this is covered by the marketing dpt by taking into account 1-1.5 mask set, where the 0-0.5 stands for several 'quick' BE mask changes. Furthermore, I feel it is disregarded that you need some level of configurability and observability to solve/test issues that can make your chip successful within that extra 0.5 mask. This means extra IC real estate conflicting with the 'Size matters part'. Without such testability, it really becomes a card game, since in that case a nonfunctional chip sends you back to square 1, as you cannot observe (or tune around) the problem.

Title: Re: Competitive Chip Design - A "must read" for all designers.
Post by loose-electron on Oct 22nd, 2012, 11:04am

Lex:

Debug access is important in R&D I do agree.

But if you have a final product where you are 30% higher in cost due to
die size increases associated with debug, it will not sell.

Thanks for the feedback!
Jerry

Title: Re: Competitive Chip Design - A "must read" for all designers.
Post by carlgrace on Nov 8th, 2012, 1:17pm

This was a really good article.  Takes me back to my earlier days in the trenches of high-volume IC design.  I particularly appreciated the Just Good Enough constraint.  There was a great line in the book Soul of a New Machine where Tom West says: "Not everything worth doing is worth doing well".  Part of the art of good IC design is knowing where a quick-and-dirty job will work and where you really have to stand on your head to meet a hard spec.

To Lex's comment, in my personal experience the dev plan always (usually) includes a test chip with all the knobs and test busses and the like to get your observability.  The core functionality and performance of the circuit is verified, the design is centered, and then the most of the test functionality is purged for the final version.  In this way you can, to some extent, have your cake and eat it too.

One other point is that Jerry's article was intended for high-volume stuff.  For a low-volume ASIC (like the kind I design now) that tunability and testability stays in the chip through production, since the cost driver is NRE, not wafers.

Title: Re: Competitive Chip Design - A "must read" for all designers.
Post by loose-electron on Nov 14th, 2012, 4:12pm


carlgrace wrote on Nov 8th, 2012, 1:17pm:
This was a really good article.  Takes me back to my earlier days in the trenches of high-volume IC design.  I particularly appreciated the Just Good Enough constraint.  There was a great line in the book Soul of a New Machine where Tom West says: "Not everything worth doing is worth doing well".  Part of the art of good IC design is knowing where a quick-and-dirty job will work and where you really have to stand on your head to meet a hard spec.

To Lex's comment, in my personal experience the dev plan always (usually) includes a test chip with all the knobs and test busses and the like to get your observability.  The core functionality and performance of the circuit is verified, the design is centered, and then the most of the test functionality is purged for the final version.  In this way you can, to some extent, have your cake and eat it too.

One other point is that Jerry's article was intended for high-volume stuff.  For a low-volume ASIC (like the kind I design now) that tunability and testability stays in the chip through production, since the cost driver is NRE, not wafers.


Low volume chips are the exception rather than the rule, so you are lucky enough to operate in a special space.

For low volume stuff I tell the customer to do a PCB instead, some places that doesn't fly so it becomes big buck to do small volume chips.

Soul of a New Machine! That's going back a bit...

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