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Design Languages >> Verilog-AMS >> Cannot generate ahdl_include in netlist by ADE
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Message started by Daniel Lai on Oct 31^st, 2012, 4:57am

Title: Cannot generate ahdl_include in netlist by ADE
Post by Daniel Lai on Oct 31^st, 2012, 4:57am

dear AMS experts,

I met a problem about the ADE compiler failed when simulating test circuit with verilog A macro. And the problem is the generated netlist lost ahdl_include "***.va".

My simulation environment is:
a. Spectre/MMSIM10.0
b. ADE
c. The switch view includes: veriloga, ahdl

Please kindly advise if any comment, thanks.
Daniel Lai