The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Layout of Big MOSFETs in Virtuoso Layout XL
https://designers-guide.org/forum/YaBB.pl?num=1351774957

Message started by Flynn Rider on Nov 1^st, 2012, 6:02am

Title: Layout of Big MOSFETs in Virtuoso Layout XL
Post by Flynn Rider on Nov 1^st, 2012, 6:02am

Dear all,

I am working in weak inversion regime and in order to suppress the flicker noise I have to keep width of input differential PMOS at 800u. But the layout of this MOS is area inefficient. (FIG 1)

When I use the "multiplier" parameter in the properties of this MOS and value it at 16, it generates 16 layout instances with 50um width.

(FIG 2)

When i use the "finger" parameter with the same value it generates one instance with 15 gate sections surronded by a drain and source terminal.(FIG 3)

My questions are:

1) Which one of these parameters is better to use, multiplier or figers for the better sizing of MOS?

2)I am working in analog domain, when i use multiplier paramter it creates 15 MOS in parallel which would distort the required response of the input differential pair. I mean to say when i put 16 MOS of 50um each instead of 1 800um MOS, current gets divided, transconductance changes and it barely acts as an amplifier. Pluse, it gives me errors in LVS check! So i dont think we must use multiplier parameter in analog layouts.

3) When i use finger parameter, it again gives me error in LVS check. Is there anything I can do? In fingers, 16 MOS are not held in paralle rather only the gate poly gets divided which could be shorted and not be much of problem in analog domain. But why an LVS error?

Thanks