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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> current limiter https://designers-guide.org/forum/YaBB.pl?num=1353399755 Message started by fgcsk on Nov 20th, 2012, 12:22am |
Title: current limiter Post by fgcsk on Nov 20th, 2012, 12:22am Hi all, I just wrote a current limiter. It works but the result is a little bit strange. Code:
![]() Given the input voltage(top fig.) and a series resistor, the current(bottom fig.) limits at 3mA. But I don't know why the current is somewhat distorted before it reaches the limit? Thanks. |
Title: Re: current limiter Post by boe on Nov 20th, 2012, 3:22am fgcsk, Most likely, this is a plotting artefact caused by widely-spaced simulator time points. By the way, your implementation is not recommended. A better implementation can be found at http://www.designers-guide.org/VerilogAMS/ - B O E |
Title: Re: current limiter Post by fgcsk on Nov 20th, 2012, 7:09am boe wrote on Nov 20th, 2012, 3:22am:
Above is .tran 1us 32us Even if I change it to .tran 0.01us 32us, it still have the same problem: ![]() |
Title: Re: current limiter Post by Ken Kundert on Nov 20th, 2012, 11:19am If you want to resolve the corners you will need to add a cross function. If you have access to my book on Verilog-AMS, I recommend you take a look at sections 6.2 and 6.3 (page 71-73). -Ken |
Title: Re: current limiter Post by fgcsk on Nov 20th, 2012, 1:03pm Ken Kundert wrote on Nov 20th, 2012, 11:19am:
I've tried that. But it doesn't solve the problem. :'( Actually I think the problem doesn't happen right at corners. |
Title: Re: current limiter Post by boe on Nov 20th, 2012, 2:50pm Ken Kundert wrote on Nov 20th, 2012, 11:19am:
the model is a limiter, so it should never cross the limit. - B O E |
Title: Re: current limiter Post by Ken Kundert on Nov 20th, 2012, 5:44pm Both Boe and I are trying to point you to the answer without having to spend a lot of time trying to explain a somewhat confusing topic. So, you should look at the model that BOE pointed you to (the current limited voltage regulator on the Verilog-AMS page) and if you do not understand it you should read the section of my book that I pointed you to. -Ken |
Title: Re: current limiter Post by fgcsk on Nov 28th, 2012, 12:07am I finally solved this problem. Here's the code: Code:
By using a way similar to the diode model(p73, Ken's book), I cut on a diagonal in the IV plane and get the condition: I(in,out)+V(in,out) > imax, then the problem could be solved. But I still don't know why I should not cut twice as before: I(in,out) >= imax && V(in,out) >= 0. Does it cause convergence problems? thanks. |
Title: Re: current limiter Post by boe on Nov 28th, 2012, 2:44am fgcsk wrote on Nov 28th, 2012, 12:07am:
- B O E |
Title: Re: current limiter Post by fgcsk on Nov 28th, 2012, 8:32am boe wrote on Nov 28th, 2012, 2:44am:
Could you illustrate this more detailedly? Didn't get it :-? |
Title: Re: current limiter Post by boe on Dec 5th, 2012, 4:46am fgcsk wrote on Nov 28th, 2012, 8:32am:
I'll try. For example: Suppose you are at V(in,out) = 1 Volt and I(in, out) = imax. Then the model should use the current path. If I(in,out) now changes to imax-ε due to numerical errors, your first model jumps to V(in, out) = 0 creating a discontinuity. This discontinuity is not only wrong (in this case), but can also cause convergence difficulties. - B O E |
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