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Simulators >> Circuit Simulators >> nan appears in stb analysis
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Message started by optimized on Dec 10^th, 2012, 2:06pm

Title: nan appears in stb analysis
Post by optimized on Dec 10^th, 2012, 2:06pm

SA,
when I perform an stb analysis in cadence for PLL model I have made using verilog-a i get (nan ) in all the fields of stability
I am putting the Iprobe between the VCO block & the divider block & I am selecting it as a probe of instance
I am sure there is some thing wrong but I do not know which is wrong

Title: Re: nan appears in stb analysis
Post by tulip on Dec 17^th, 2012, 5:06pm

I think this happens because VCO is already oscillate, I suggest you substitute VCO with a model which describes voltage - frequency realtionship and also the PFD should be substituted with a model.

Title: Re: nan appears in stb analysis
Post by sheldon on Dec 22^nd, 2012, 9:14pm

Optinmized,

You have not provided enough information to comment is detail. Some
observations assuming this comment is based on a time domain model:
1) A PLL is a fairly complex system, how are going about defining an
operating point? It would probably need to be based on a periodic
steady state. However, unless the design is an Integer-N PLL with a
low divide ratio, then this is not possible.
2) If you can get a periodic steady-state, then the question becomes how
are you modeling the components in the PLL. Unless their contribution
to excess is correctly modeled, then it is unlikely that stability
analysis will return the results you are looking for.

Best Regards,

Sheldon