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Design >> Mixed-Signal Design >> MAx decap value
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Message started by summi on Dec 11^th, 2012, 3:02am

Title: MAx decap value
Post by summi on Dec 11^th, 2012, 3:02am

Dear forum,
Can any one tell me how to How deside decap for chip, i know it is very difficult to predict, but how to come up with a rough number. Recently i have joined IC design job, there i have seen people are filling all gaps with decaps while taping out the chip. So i like to know what limit the max value of the cap.

Br,
Summi.

Title: Re: MAx decap value
Post by raja.cedt on Dec 11^th, 2012, 4:24pm

It depends on many factors, some time(many times) decap helps to reduce the impact of switching noise. May be resonance frequency(which is larger than signal frequency) between bond wire inductance and decap will place the upper limit. For flip chip there is no this kind of limit.

Some experienced people will find dynamic power of the chip and estimate Ceffective from Cv^2f formula.

Thanks,
Raj.

Title: Re: MAx decap value
Post by loose-electron on Feb 8^th, 2013, 6:51pm

Inside the chip capacitinace should be sufficient for power decoupling at frequencies where interconnect inductance to the outside world does not allow you to do it with external capacitors.

Go figure out the inductance of your leadframe and bond wires.

Title: Re: MAx decap value
Post by Erez_Sarig on Feb 8^th, 2013, 11:11pm

Answer is simple:
As no one design the die size based on Decap values needed + the Decap are needed to reject any ripple on supplies, the value of Decap needed is:
As much as you can where ever you can. But note to have also Taps to GND as they are improtant also.
Later you can simulate Fullchip with package model and see effect just note that PCB trace most of the time have higher inductance as minimum lenght of pcb trace is ~2mm which is ~2nH-5nH.

Erez Sarig