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Design >> Analog Design >> Power transistor layout for LDO
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Message started by Multicathode on Dec 14^th, 2012, 1:21pm

Title: Power transistor layout for LDO
Post by Multicathode on Dec 14^th, 2012, 1:21pm

Hi Guys,

I designed an LDO for 120mA max load current. The size of the power transistor is 60mm. Does anyone know if this is normal and if its normal then how do I layout a 6 cm transistor? Can anyone suggest me some good references (book , paper etc)

Thanks

Title: Re: Power transistor layout for LDO
Post by raja.cedt on Dec 14^th, 2012, 2:09pm

hello,
looks so huge, why did you chosen such huge one, any special purpose?

Is your architecture is one opamp with pmos pass transistor or any thing else?

Thanks,
Raj.

Title: Re: Power transistor layout for LDO
Post by Multicathode on Dec 14^th, 2012, 2:45pm

I calculated the width to be around 40mm in 0.35 um technology with minimum length. I need a dropout voltage of 0.2V. Initially I could not meet the dropout spec so I just keep on increasing the width to meet the dropout spec at full load.

I am using a buffer between the error amp and power pmos to drive the pmos. The buffer also aids in stability.

I am not sure if its the best approach but yes this is what I did.

Thanks

Title: Re: Power transistor layout for LDO
Post by raja.cedt on Dec 14^th, 2012, 2:57pm

i guess pmos input is Quite high, try to increase Vgs rather increasing width, this can be done by redesigning opamp output common mode.

Show me your ckt....

Thanks,
Raj.

Title: Re: Power transistor layout for LDO
Post by Multicathode on Dec 16^th, 2012, 4:45pm

Hi Raj

I am implementing this paper.

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=4277856&contentType=Journals+%26+Magazines&searchField%3DSearch_All%26queryText%3Dbuffer+impedance+attenuation

Thanks

Title: Re: Power transistor layout for LDO
Post by loose-electron on Dec 18^th, 2012, 4:51pm

Your power transistor is going to be broken up into multiple parallel devices, general by using "multiple fingers"

(often "NF=xx parameter on the transistor)

Cautions:

Get a rough estimate of the gate resistance (not in transistor model)
and make sure that the Cgs, Cgd, Cgate-elsewhere do not play into an
RC constant along the gate of the long gate stripe that is the W of the transistor.

That may limit the max W that you use in the transistor.

Connect the gate driver circuit to both ends of the gate stripe.

Also, the NF number may be limited by how far apart you can space the NWell contacts.
A large NF and a large W leads to a large NWell under the transistor. Check the design rules for
how large you can make the NWell.

That may require use of "M=" for multiple devices where devices are separated by well contacts.

Balance the resistive metal paths from each part of the transistor
so the IR drops balance and give equal current density
in the transistor.

That's what I can immediately think of.

Title: Re: Power transistor layout for LDO
Post by grosser on Dec 19^th, 2012, 3:08am

I agree with loose-electron

You can try draw core transistor with a few fingers and then place it in a XY matrix.

Or you can draw something similar to http://ims.unipv.it/Microelettronica/Layout02.pdf page 23 if you accept inaccuracy.

regards
grosser

Title: Re: Power transistor layout for LDO
Post by raja.cedt on Dec 19^th, 2012, 5:56am

hello grosser ,
Is it posb to extract this structure, because it is not an standard pcell, that's why i am asking.

Thanks,
Raj.

Title: Re: Power transistor layout for LDO
Post by analog_wiz on Dec 21^st, 2012, 2:43am

split the power transistor into reasonable no of fingers and run EM/IR checks on the output Vregout node which will carry 150mA. Also no of fingers should be calculated keeping in mind the source drain resistances of unit pcell transistors and the EM requirements.Conclusion:run a IR drop sim or run an extracted sim with power /gnd extraction included.

Title: Re: Power transistor layout for LDO
Post by Dan Clement on Dec 30^th, 2012, 12:10pm

Why not push the power transistor off chip? Power Qs are cheap and at the size you are talking about it may begin to make sense.

If you can't do that you are stuck doing a custom layout. There are numerous issues including latch up, ESD, thermal, metal migration, yield, modeling, parasitic thyristors, etc.

If you don't understand all of these issues and mitigate the risks you will get burned.

I have seen some guys use multiple voltage regulators in parallel to make the stability a little easier. I also saw one person put a switch mode supply in parallel with an LDO.

I have also seen a few papers about using the gate RC as part of the stability.

For all things linear regulator check out Rincon-Mora's work.