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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Bug or nor not a bug in table_model https://designers-guide.org/forum/YaBB.pl?num=1355675676 Message started by RolfK on Dec 16th, 2012, 8:34am |
Title: Bug or nor not a bug in table_model Post by RolfK on Dec 16th, 2012, 8:34am Dear Experts, I'm not sure if I run into a bug or did not understand the LRM. SimVison gave me a very hard time (chrashed) before I could figure out the root cause. Please see belows test lines commented with OK or NG. my table data is the same as in the LRM 2.3.1 Code:
My trial lines are below: Code:
It looks like if the isoline (first arg) is passed a integer string I run into problems. I have alos tested a variable as arg 1 which was defined as interger. This leads to the same fail. The LRM says: Quote:
For a string integer this is may be not applicable, but if I pass a variable nad the function expects a real implicit conversion schould take place. Could sameone confirm that this is really a bug and not a wrong usage of AMS by myself ? Thanks a lot RolfK |
Title: Re: Bug or nor not a bug in table_model Post by Geoffrey_Coram on Dec 17th, 2012, 8:03am I agree with you that this is a bug in the simulator. |
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