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Design >> Mixed-Signal Design >> sampling clock jitter stand for？
https://designers-guide.org/forum/YaBB.pl?num=1355819213

Message started by 880321 on Dec 18^th, 2012, 12:26am

Title: sampling clock jitter stand for？
Post by 880321 on Dec 18^th, 2012, 12:26am

Hi，

I am desig a PLL for an ADC, and the ADC has spec of clk jitter;

from PLL design I can get the PLL out phase noise L(f)

int(L(f))------>can get phase jitter, namely edge-to-edge jitter;

does this phase jitter is the sampling clk jitter i need to meet?

from ADI app note MT-008, the clk time jitter is the phase jitter ;

but
http://www.designers-guide.org/Forum/YaBB.pl?num=1260769814

give different idea

anybody know the exact answer?

Title: Re: sampling clock jitter stand for？
Post by Virvasav on Jan 2^nd, 2013, 11:05pm

Hi,

PLL has two types of jitter random and deterministic. The jitter you got from phase noise is random. For the spec of ADC, it includes random as well as deterministic both. For deterministic jitter you have to measure, period jitter or cycle to cycle jitter.