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Design Languages >> Verilog-AMS >> sformat equivalent in Verilog-A
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Message started by ShawnR on Jan 3^rd, 2013, 6:48am

Title: sformat equivalent in Verilog-A
Post by ShawnR on Jan 3^rd, 2013, 6:48am

I am trying to convert a real to a string in Verilog-A. In Verilog I would use sformat.
Any ideas how to do it in Verilog-A?
Shawn

Title: Re: sformat equivalent in Verilog-A
Post by Geoffrey_Coram on Jan 7^th, 2013, 5:53am

What do you intend to do with the string afterwards? Most simulators that support Verilog-A allow you to $strobe or $display with the usual C-style formatting (%e or %f), if you want to output the string. Many simulators also support $fstrobe.