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Design >> RF Design >> pll vco control voltage in simulink
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Message started by mixed_signal on Jan 7^th, 2013, 6:07pm

Title: pll vco control voltage in simulink
Post by mixed_signal on Jan 7^th, 2013, 6:07pm

Hi,
i simulated my pll using simulink n time domain and ended up with peculiar control voltage even with 60 deg/75deg PM.

Fig 1 shows the output of loop filter. Fig. 2 shows output after VDD saturation. I want my vco control voltage to slightly rise from 0 at t=0 and settle as if critically damped.

Is it due very small ref frequency and high N=2500
fref=400khz fout=1Ghz N=2500

Title: Re: pll vco control voltage in simulink
Post by mixed_signal on Jan 7^th, 2013, 6:09pm

fig1

Title: Re: pll vco control voltage in simulink
Post by mixed_signal on Jan 7^th, 2013, 6:10pm

fig2

Title: Re: pll vco control voltage in simulink
Post by raja.cedt on Jan 10^th, 2013, 4:40am

Hello,
There is some thing went wrong in calculations or loop Bandwidth higher than Gadner limit (Fref/10). Show me loop parameters like Icp, Kvco and filter element.

Thanks,
Raj.

Title: Re: pll vco control voltage in simulink
Post by mixed_signal on Jan 15^th, 2013, 5:03pm

Hi Raja! Thanks for the favour!

I have the new specs as follows but I still get almost the same response:

fout=800Mhz
fref=333.3khz
loop bw=33.3khz
Kvco=20mhz/volt
Icp=50uA
C1=2.5pF
C2=32.9pF
R2=541k

Title: Re: pll vco control voltage in simulink
Post by BackerShu on Jan 15^th, 2013, 9:19pm

Hello mixed_signal,

How do you know the PM in your real model? (Not from the calculation.)
Did you check the actual loop delay?

Title: Re: pll vco control voltage in simulink
Post by raja.cedt on Jan 16^th, 2013, 2:08am

Hello,
@Mixed signal,
Your Filter resistance is too high, with this you can't charge loop filter, Voltage drop across that is around 10V. So please reduce this resister value to few kilo ohms by adjusting Icp. And also please recalculate gardner limit by using attached doc. Bw is exactly Fref/10, if you dont have any problem with settling go even below.

@BackerShu,
here divider delay and some other components response time doesn't matter much. Acceptable loop delay without effecting time domain response is .367/(loopBW) is around 2usec in the present case. I don't think getting 2usec delay is common.

Title: Re: pll vco control voltage in simulink
Post by mixed_signal on Jan 16^th, 2013, 8:16pm

Hi raja.cedt,
I cant play with current since I have low power constraint.
current is inversly prop with R so to reduce R from 500k to 50k I have to increase current to 500uA which is not possible.

Hi backer,
I am talking abt PM from calculation

Title: Re: pll vco control voltage in simulink
Post by BackerShu on Jan 16^th, 2013, 9:03pm

mixed_signal wrote on Jan 16^th, 2013, 8:16pm:

I cant play with current since I have low power constraint.
current is inversly prop with R so to reduce R from 500k to 50k I have to increase current to 500uA which is not possible.

If you have to keep the product of Icp*R constant, the ripple in control voltage is really big even if the PLL can reach steady state. I think that's what Raja worried about.

If the bandwidth is fixed, you need to think whether the Kvco you have in the simulation is reasonable or not.

mixed_signal wrote on Jan 16^th, 2013, 8:16pm:

I am talking abt PM from calculation

In actual model it might be smaller. This might not be the reason, as Raja mentioned, there is some tolerance for the loop delay. But you can check to rule this out.

Title: Re: pll vco control voltage in simulink
Post by raja.cedt on Jan 17^th, 2013, 12:07am

Then you have only one option, redesign VCO. Looks like you have very small Kvco, with generic vco architectures (mainly ring VCO) you could get Kvco min 1Ghz/V. Try this.

If you can't do this then go for dual loop pll(which is having many degree of freedoms) rather conventional loop filter

Thanks,
raj.

Title: Re: pll vco control voltage in simulink
Post by mixed_signal on Jan 26^th, 2013, 9:59am

Hi,
1. I have attached transient response of the control voltage of my PLL in Cadence. This is NOT behavioral reponse.

2. From t=0 to 100us it is the startup time. No frequency step provided

3. At t=170us a frequency step of 40MHz (max size for the pll) is provided and resulting transient response is shown.

The startup response saturates to VDD and then settles. Is this a problem?

Is the freq step response OK for phase margin of 60 deg.

Title: Re: pll vco control voltage in simulink
Post by raja.cedt on Jan 26^th, 2013, 3:51pm

Hello,
Looks like some thing seriously went wrong in the filter design, that's why some weird start-up, it is dangerous some times just because vctl is saturating and may turn of charge pump. But frequency settling looks okay, though there is some ringing (some part is cycle slipping). Did you modified your charge-pump current (as i suggested earlier), though you don't have power margin just try that (some how reduce the BW) and see the response. Since you have 33.33khz BW, your loop should settle in 4*tau, which is around 120us but your settling looks pretty faster than this.

Even if you have any problem with settling, due to less Phase margin magnitude response might have few db peaking which amplifies your jitter, so it all depends on which kind application you are targeting.

Title: Re: pll vco control voltage in simulink
Post by BackerShu on Jan 27^th, 2013, 11:25am

Hello mixed_signal,

Actually, I think this might not be a big issue at the initial settling. It may be just related to some initial phase condition and frequency offset when the PLL starts.
Can you try to change the initial phase of reference clock, and run the system again. I think you will get different behaviors for initial settling.