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Design Languages >> Verilog-AMS >> Ideal diode model in VerilogA/MS
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Message started by Dushyant Juneja on Jan 7^th, 2013, 11:56pm

Title: Ideal diode model in VerilogA/MS
Post by Dushyant Juneja on Jan 7^th, 2013, 11:56pm

Hi,
Just wondering about the listing 21 (chap 3, pg. 73) of Ken's Designer's guide to Verilog-AMS... can't we have a model core like this for the ideal diode:

Code:

if(V(a,c)<0)
I(a,c) <+ 0;
else
V(a,c) <+ 0;

This model takes care of the boundary where V(a,c)=0 and diode is on. One need not go with the rather strange condition like V(a,c)+I(a,c). I agree that V(a,c)+I(a,c) is required for crossing point detection, but is it a necessary if clause condition? I couldn't relate with it in the previous listing 20 for ideal mechanical stop either.

I doubt if I am going illegal in the above syntax, probably because of probing potential at a branch where I am assigning flow. But in listing 21, both potential and flow are probed (to my surprise). So, this should probably be legal.

No doubt I am a beginner, so am seeking guidance. Any comments?

* [timestamp=1357631631]

Title: Re: Ideal diode model in VerilogA/MS
Post by Frank Wiedmann on Jan 8^th, 2013, 8:06am

Take a look at chapter 3 "AMS Behavioral Modeling" of the Mixed-Signal Methodology Guide, which is available in four pdf files from http://www.eetimes.com/electronics-blogs/eda-designline-blog/4397605/Book-excerpt--Mixed-signal-methodology-guide-part-4. For your question, the section "Analog Best Practices" from http://www.eetimes.com/ContentEETimes/Documents/EDA-Designline/MS-Part4.pdf is particularly relevant.

Title: Re: Ideal diode model in VerilogA/MS
Post by Dushyant Juneja on Jan 23^rd, 2013, 5:39am

Hi Frank,

Thanks for the reply. Pardon me I was busy with some company work so could not reply immediately.

I am not sure about what you are trying to point at. Is it about the abrupt change in V(a,c) that you are pointing at? Could you please further a hint?

Dushyant

Title: Re: Ideal diode model in VerilogA/MS
Post by Ken Kundert on Jan 23^rd, 2013, 1:08pm

When the switch is on your are driving the voltage with 0. The problem is that the simulator does not use that value directly. It uses it when it solves the large system of equations to calculate the actual switch voltage, which will only approximate 0. Furthermore it the calculation is iterative. Assume that when the switch is on it calculates that the voltage is -1aV for an iteration. This turns the switch off. If you assume the value computed has a very small random component centered at 0, then the act of turning the switch on actually causes it to turn off roughly half the time with your model. This leads to convergence problems.

Effectively, an ideal model innately has a cliff and by writing the model the way you did you are causing the simulator to always walk along the edge of the cliff. By adding the current term, the simulator steps away from the cliff and so is unlikely to fall off inadvertently.

-Ken

Title: Re: Ideal diode model in VerilogA/MS
Post by Dushyant Juneja on Jan 27^th, 2013, 10:23pm

Hi Ken,

Thanks for the vivid explanation. I got the concept.

Just to clarify a little more, is it valid to probe current at a branch where I am assigning flow? I see you have done that as well in the diode model of listing 21. What confuses me, is as to whether it violates the rule that one cannot probe current in a potential branch, and vice versa. What kind of branch, should this diode be called, then?

Thanks again for your help.

* [timestamp=1359354208]

Title: Re: Ideal diode model in VerilogA/MS
Post by Ken Kundert on Jan 28^th, 2013, 8:39am

There are 5 types of branches in Veilog A:
Potential source branches: drive the branches potential, may access either its potential or its flow
Flow source branch: drive the branches flow, may access either its potential or its flow
Potential probe branch: only observe a branches potential (branch is undriven), may not also observe its flow
Flow probe branch: only observe a branches flow (branch is undriven), may not also observe its potential
Switch branch: alternate between driving branches potential and flow, may observe either its potential or flow.

So the only real restriction here is on probe branches, and the reason is because if you were to probe both the voltage and the current of a branch without driving it, Verilog-A could not determine whether it was a voltage probe or a current probe, and those two are modeled quite differently. A voltage probe is modeled as an open and a current probe is modeled as a short. So fundamentally its not a problem that you can only observe one type of quantity on a probe branch because by definition the other is zero.

-Ken

Title: Re: Ideal diode model in VerilogA/MS
Post by Dushyant Juneja on Jan 28^th, 2013, 9:44pm

Hi Ken,

Thanks again. That clarifies my doubt more than enough. Looking forward to more communications over such topics.

/me