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Design >> Analog Design >> Is this OP stable?
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Message started by kane on Jan 8^th, 2013, 9:52pm

Title: Is this OP stable?
Post by kane on Jan 8^th, 2013, 9:52pm

Hi, all.

I am designing an 10dB BPF. But I find the phase margin of the OP is good at point A but poor at point B.
If this BPF is stable?

I think it is stable ? But not very sure.

Title: Re: Does the OP is stable
Post by kane on Jan 8^th, 2013, 9:52pm

the phase margin of the OP at point B (at the output of the OP)

Title: Re: Is this OP stable?
Post by raja.cedt on Jan 8^th, 2013, 11:11pm

Hello,
Where did you break the loop?? How did you find Phase margin. Use STB for better results.

Thanks,
Raj.

Title: Re: Does the OP is stable
Post by buddypoor on Jan 9^th, 2013, 12:21am

kane wrote on Jan 8^th, 2013, 9:52pm:

the phase margin of the OP at point B (at the output of the OP)

You cannot determine the margin at a particular "point".
The phase margin is found by simulating the open-loop response.

Title: Re: Is this OP stable?
Post by kane on Jan 9^th, 2013, 5:44pm

Thank you ,very much.

Using STB, get the phasemargin is 35. Is that result OK?

Title: Re: Is this OP stable?
Post by raja.cedt on Jan 9^th, 2013, 11:22pm

hello,
Please refer basic book on control systems, you need at least 60 if good step Responce is your concern or around 52 (theoretical) if settling time is your concern with small ringing.
Thanks.
Raj

Title: Re: Is this OP stable?
Post by Erez_Sarig on Feb 7^th, 2013, 1:14pm

Hi,
it looks like your stability test OK. (As long as the input capacitor exists in the schematic for real. it Yes so you have good PM.
Cadence allow you to use STB simulation which do it for you.

Erez

Title: Re: Is this OP stable?
Post by loose-electron on Feb 8^th, 2013, 6:40pm

35 degrees? Too little phase margin in my opinion.

Expect it to ring in the time domain.

Try a time domain closed loop simulation and see how it responds to a step input.

Also, check it over process corners and it will probably be even less.
Also check it with both high and low common mode input too.

Title: Re: Is this OP stable?
Post by threepwood on Mar 23^rd, 2013, 5:45am

kane wrote on Jan 8^th, 2013, 9:52pm:

Hi, all.

I am designing an 10dB BPF. But I find the phase margin of the OP is good at point A but poor at point B.
If this BPF is stable?

I think it is stable ? But not very sure.

From your Open Loop AC signal ( called OL(s) )
Create a formula in your calculator: CL(s) = OL(s) / ( 1+OL(s) ) and probe the amplitude in dB20 of this complex expression. If you see any overshoot somewhere, you can consider your circuit is not robustly stable, and if you see a significant peaking you can consider it is unstable.
Then add the phase of CL(s): if you see the amplitude decrease while phase increases, it means you have complex poles with positive real part: it means your loop is totally unstable.

Now the question is: what do you mean by "is it stable?"
a 35deg phase margin circuit is stable "mathematically speaking" because it will converge at t=infinity, but will have lots of ringing.

In all cases, the best test to do is to perform a transient simulation with a step stimuli on the input.